Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10219387 | Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate | Leilei Zhang, Ronilo Boja, Zuhair Bokharey | 2019-02-26 |
| 10096534 | Thermal performance of logic chip in a package-on-package structure | Jayprakash Chipalkatti, Shantanu Kalchuri | 2018-10-09 |
| 10032692 | Semiconductor package structure | Shantanu Kalchuri, Brian Schieck | 2018-07-24 |
| 9831184 | Buried TSVs used for decaps | — | 2017-11-28 |
| 9760132 | Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad | Leilei Zhang, Ron Boja, Zuhair Bokharey | 2017-09-12 |
| 9728481 | System with a high power chip and a low power chip having low interconnect parasitics | Joe Greco, Jun Zhai, Joseph Minacapelli, John Chen | 2017-08-08 |
| 9716051 | Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity | Leilei Zhang, Ron Boja, Zuhair Bokharey | 2017-07-25 |
| 9659815 | System, method, and computer program product for a cavity package-on-package structure | Ronilo Boja, Teckgyu Kang | 2017-05-23 |
| 9570284 | Method and system for controlling a semiconductor fabrication process | — | 2017-02-14 |
| 9530714 | Low-profile chip package with modified heat spreader | Shantanu Kalchuri, Leilei Zhang | 2016-12-27 |
| 9379202 | Decoupling capacitors for interposers | — | 2016-06-28 |
| 9368422 | Absorbing excess under-fill flow with a solder trench | Leilei Zhang, Ron Boja, Zuhair Bokharey | 2016-06-14 |
| 9087830 | System, method, and computer program product for affixing a post to a substrate pad | Leilei Zhang, Shantanu Kalchuri, Zuhair Bokharey | 2015-07-21 |
| 8618651 | Buried TSVs used for decaps | — | 2013-12-31 |
| 7964422 | Method and system for controlling a semiconductor fabrication process | — | 2011-06-21 |
| 6093936 | Integrated circuit with isolation of field oxidation by noble gas implantation | Sheldon Aronowitz, Yu-Lam Ho | 2000-07-25 |
| 5917207 | Programmable polysilicon gate array base cell architecture | Michael J. Colwell, Teh-Kuin Lee, Jane C.T. Chiu, Stanley Yeh, Gobi R. Padmanabhan | 1999-06-29 |
| 5874754 | Microelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gates | Jasopin Lee, Gobi R. Padmanabhan, Stanley Yeh | 1999-02-23 |
| 5796130 | Non-rectangular MOS device configurations for gate array type integrated circuits | Tim Carmichael, Gobi R. Padmanabhan, Stanley Yeh | 1998-08-18 |
| 5777383 | Semiconductor chip package with interconnect layers and routing and testing methods | Mark Phillip Stager, Gobi R. Padmanabhan | 1998-07-07 |
| 5723896 | Integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrate | Sheldon Aronowitz | 1998-03-03 |
| 5721151 | Method of fabricating a gate array integrated circuit including interconnectable macro-arrays | Gobi R. Padmanabhan | 1998-02-24 |
| 5691218 | Method of fabricating a programmable polysilicon gate array base cell structure | Michael J. Colwell, Teh-Kuin Lee, Jane C.T. Chiu, Stanley Yeh, Gobi R. Padmanabhan | 1997-11-25 |
| 5679598 | Method of making a CMOS dynamic random-access memory (DRAM) | — | 1997-10-21 |
| 5648290 | Method of making a CMOS dynamic random-access memory (DRAM) | — | 1997-07-15 |