Issued Patents All Time
Showing 25 most recent of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12040262 | Flex board and flexible module | Dennis R. Pyper, Lan H. Hoang | 2024-07-16 |
| 12041728 | Selective soldering with photonic soldering technology | Maryam Rahimi, Meng Chi Lee, Wyeman Chen, Jason P. Marsh, Lan H. Hoang +1 more | 2024-07-16 |
| 11550975 | Methods and systems for predicting interfacial tension of reservoir fluids using downhole fluid measurements | Sharath Chandra Mahavadi, Robin Singh, Wael Abdallah, Mohammed Fadhel Al-Hamad, Bastian Sauerer +1 more | 2023-01-10 |
| 11462461 | System in package for lower z height and reworkable component assembly | Lan H. Hoang | 2022-10-04 |
| 10602612 | Vertical module and perpendicular pin array interconnect for stacked circuit board structure | Lan H. Hoang, Takayoshi Katahira, Raghunandan Chaware | 2020-03-24 |
| 10219387 | Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate | Ronilo Boja, Abraham Yee, Zuhair Bokharey | 2019-02-26 |
| 9831189 | Integrated circuit package with a conductive grid formed in a packaging substrate | — | 2017-11-28 |
| 9760132 | Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad | Ron Boja, Abraham Yee, Zuhair Bokharey | 2017-09-12 |
| 9716051 | Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity | Ron Boja, Abraham Yee, Zuhair Bokharey | 2017-07-25 |
| 9530714 | Low-profile chip package with modified heat spreader | Shantanu Kalchuri, Abraham Yee | 2016-12-27 |
| 9502355 | Bottom package having routing paths connected to top package and method of manufacturing the same | — | 2016-11-22 |
| 9478482 | Offset integrated circuit packaging interconnects | Zuhair Bokharey | 2016-10-25 |
| 9385098 | Variable-size solder bump structures for integrated circuit packaging | Zuhair Bokharey | 2016-07-05 |
| 9368422 | Absorbing excess under-fill flow with a solder trench | Ron Boja, Abraham Yee, Zuhair Bokharey | 2016-06-14 |
| 9368439 | Substrate build up layer to achieve both finer design rule and better package coplanarity | Zuhair Bokharey | 2016-06-14 |
| 9368183 | Method for forming an integrated circuit package | — | 2016-06-14 |
| 9087830 | System, method, and computer program product for affixing a post to a substrate pad | Abraham Yee, Shantanu Kalchuri, Zuhair Bokharey | 2015-07-21 |
| 9082674 | Microelectronic package with stress-tolerant solder bump pattern | — | 2015-07-14 |
| 9059054 | Integrated circuit package having improved coplanarity | — | 2015-06-16 |
| 8410604 | Lead-free structures in a semiconductor device | Laurene Yip, Kumar Nagarajan | 2013-04-02 |
| 8143532 | Barrier layer to prevent conductive anodic filaments | — | 2012-03-27 |
| 8063656 | Method of enabling a circuit board analysis | Pedro R. Ubaldo | 2011-11-22 |
| 7994631 | Substrate for an integrated circuit package and a method of forming a substrate | — | 2011-08-09 |
| 7821132 | Contact pad and method of forming a contact pad for an integrated circuit | — | 2010-10-26 |
| 7807501 | Integrated circuit package and apparatus and method of producing an integrated circuit package | — | 2010-10-05 |