Raghunandan Chaware — 22 Patents at AMD

Raghunandan Chaware has been granted 22 US patents while listed as an inventor at AMD. The first was granted in 2008 and the most recent in July 2021. Raghunandan Chaware ranks #189,202 of 4,157,543 US inventors in our database (top 4.6%). Patent records list Raghunandan Chaware in Sunnyvale, CA, US.

Issued Patents All Time

Showing 1–22 of 22 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11075117	Die singulation and stacked device structures	Ganesh Hariharan, Inderjit Singh	2021-07-27	$80,530,000
10840192	Stacked silicon package assembly having enhanced stiffener	Nael Zohni, Shin S. Low, Inderjit Singh, Ganesh Hariharan	2020-11-17	$30,681,000
10638608	Interconnect frames for SIP modules	Lan H. Hoang, Chang Liu, Takayoshi Katahira	2020-04-28	$120,851,000
10602612	Vertical module and perpendicular pin array interconnect for stacked circuit board structure	Lan H. Hoang, Takayoshi Katahira, Leilei Zhang	2020-03-24	$68,289,000
10204841	Temporary connection traces for wafer sort testing	Matthew H. Klein	2019-02-12	$116,837,000
10032682	Multi-die wafer-level test and assembly without comprehensive individual die singulation	Matthew H. Klein, Glenn O'Rourke	2018-07-24	$14,986,000
9989572	Method and apparatus for testing interposer dies prior to assembly	Ganesh Hariharan, Amitava Majumdar	2018-06-05	$30,167,000
9865567	Heterogeneous integration of integrated circuit device and companion device	Ganesh Hariharan, Inderjit Singh, Amitava Majumdar, Glenn O'Rourke	2018-01-09	$17,814,000
9761533	Interposer-less stack die interconnect	Amitava Majumdar, Glenn O'Rourke, Inderjit Singh	2017-09-12	$86,804,000
9418909	Stacked silicon package assembly having enhanced lid adhesion	Inderjit Singh	2016-08-16	$13,047,000
9385106	Method for providing charge protection to one or more dies during formation of a stacked silicon device	Inderjit Singh, Glenn O'Rourke, Ganesh Hariharan	2016-07-05	$18,218,000
9341668	Integrated circuit package testing	Ganesh Hariharan, Glenn O'Rourke, Inderjit Singh, Eric J. Thorne, David E. Schweigler	2016-05-17
8900987	Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices	Inderjit Singh, Ganesh Hariharan, Glenn O'Rourke	2014-12-02	$18,051,000
8841752	Semiconductor structure and method for interconnection of integrated circuits	Kumar Nagarajan	2014-09-23	$12,452,000
8766086	System and method for laminating photovoltaic structures	Abhay Maheshwari	2014-07-01
8704384	Stacked die assembly	Ephrem C. Wu	2014-04-22	$13,693,000
8519528	Semiconductor structure and method for interconnection of integrated circuits	Kumar Nagarajan	2013-08-27	$3,662,000
8415783	Apparatus and methodology for testing stacked die	Arifur Rahman	2013-04-09	$2,654,000
8361259	System and method for determining placement of photovoltaic strips using displacement sensors	Shirish Shah, Frank Magana, Junaid Fatehi, Enrico Casaje	2013-01-29
7906857	Molded integrated circuit package and method of forming a molded integrated circuit package	Lan H. Hoang, Laurene Yip	2011-03-15	$21,663,000
7863092	Low cost bumping and bonding method for stacked die	Arifur Rahman	2011-01-04	$8,396,000
7338842	Process for exposing solder bumps on an underfill coated semiconductor	Christopher Dominic	2008-03-04

Raghunandan Chaware — 22 Patents

Issued Patents All Time

Patent Widget