Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
GH

Ganesh Hariharan — 7 Patents

AMD: 6 patents #1,882 of 9,280Top 25%
Santa Clara, CA: #2,368 of 9,301 inventorsTop 30%
California: #83,669 of 386,348 inventorsTop 25%
Overall (All Time): #680,018 of 4,157,543Top 20%
7 Patents All Time
Ganesh Hariharan has been granted 7 US patents while listed as an inventor at AMD. The first was granted in 2014 and the most recent in July 2021. Ganesh Hariharan ranks #680,018 of 4,157,543 US inventors in our database (top 16.4%). Patent records list Ganesh Hariharan in Santa Clara, CA, US.

Patents per Year

Patents granted per year, 2014 to 2021Bar chart with a peak of 2 patents in 2016.peak 22014: 1 patents20142016: 2 patents20162018: 2 patents20182020: 1 patents20202021: 1 patents2021

Issued Patents All Time

Showing 1–7 of 7 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
11075117 Die singulation and stacked device structures Raghunandan Chaware, Inderjit Singh 2021-07-27 $80,530,000
10840192 Stacked silicon package assembly having enhanced stiffener Nael Zohni, Shin S. Low, Inderjit Singh, Raghunandan Chaware 2020-11-17 $30,681,000
9989572 Method and apparatus for testing interposer dies prior to assembly Raghunandan Chaware, Amitava Majumdar 2018-06-05 $30,167,000
9865567 Heterogeneous integration of integrated circuit device and companion device Raghunandan Chaware, Inderjit Singh, Amitava Majumdar, Glenn O'Rourke 2018-01-09 $17,814,000
9385106 Method for providing charge protection to one or more dies during formation of a stacked silicon device Raghunandan Chaware, Inderjit Singh, Glenn O'Rourke 2016-07-05 $18,218,000
9341668 Integrated circuit package testing Raghunandan Chaware, Glenn O'Rourke, Inderjit Singh, Eric J. Thorne, David E. Schweigler 2016-05-17
8900987 Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices Inderjit Singh, Raghunandan Chaware, Glenn O'Rourke 2014-12-02 $18,051,000