Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11075117 | Die singulation and stacked device structures | Raghunandan Chaware, Inderjit Singh | 2021-07-27 |
| 10840192 | Stacked silicon package assembly having enhanced stiffener | Nael Zohni, Shin S. Low, Inderjit Singh, Raghunandan Chaware | 2020-11-17 |
| 9989572 | Method and apparatus for testing interposer dies prior to assembly | Raghunandan Chaware, Amitava Majumdar | 2018-06-05 |
| 9865567 | Heterogeneous integration of integrated circuit device and companion device | Raghunandan Chaware, Inderjit Singh, Amitava Majumdar, Glenn O'Rourke | 2018-01-09 |
| 9385106 | Method for providing charge protection to one or more dies during formation of a stacked silicon device | Raghunandan Chaware, Inderjit Singh, Glenn O'Rourke | 2016-07-05 |
| 9341668 | Integrated circuit package testing | Raghunandan Chaware, Glenn O'Rourke, Inderjit Singh, Eric J. Thorne, David E. Schweigler | 2016-05-17 |
| 8900987 | Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices | Inderjit Singh, Raghunandan Chaware, Glenn O'Rourke | 2014-12-02 |