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USPTO Patent Rankings Data through Dec 31, 2025
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Glenn O'Rourke — 12 Patents

AMD: 9 patents #1,374 of 9,280Top 15%
LSLattice Semiconductor: 1 patents #317 of 544Top 60%
SSStmicroelectronics Sa: 1 patents #3,591 of 1,676Top 215%
Gilroy, CA: #92 of 527 inventorsTop 20%
California: #51,404 of 386,348 inventorsTop 15%
Overall (All Time): #396,045 of 4,157,543Top 10%
12 Patents All Time
Glenn O'Rourke has been granted 12 US patents while listed as an inventor at AMD. The first was granted in 1996 and the most recent in July 2020. Glenn O'Rourke ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Glenn O'Rourke in Gilroy, CA, US.

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
10707138 High yield package assembly technique Shiying Xiong, Thao H. T. Vo, Felino E. Pagaduan, Qi Xiang, Xiao-Yu Li 2020-07-07 $46,357,000
10032682 Multi-die wafer-level test and assembly without comprehensive individual die singulation Matthew H. Klein, Raghunandan Chaware 2018-07-24 $14,986,000
9865567 Heterogeneous integration of integrated circuit device and companion device Raghunandan Chaware, Ganesh Hariharan, Inderjit Singh, Amitava Majumdar 2018-01-09 $17,814,000
9761533 Interposer-less stack die interconnect Raghunandan Chaware, Amitava Majumdar, Inderjit Singh 2017-09-12 $86,804,000
9385106 Method for providing charge protection to one or more dies during formation of a stacked silicon device Raghunandan Chaware, Inderjit Singh, Ganesh Hariharan 2016-07-05 $18,218,000
9372956 Increased usable programmable device dice Yuezhen Fan, Eric J. Thorne, Xiao-Yu Li, Stephen M. Trimberger 2016-06-21 $19,025,000
9341668 Integrated circuit package testing Ganesh Hariharan, Raghunandan Chaware, Inderjit Singh, Eric J. Thorne, David E. Schweigler 2016-05-17
9214433 Charge damage protection on an interposer for a stacked die assembly Qi Xiang, Xiao-Yu Li, Cinti X. Chen 2015-12-15 $13,307,000
8900987 Method for removing bumps from incomplete and defective interposer dies for stacked silicon interconnect technology (SSIT) devices Inderjit Singh, Raghunandan Chaware, Ganesh Hariharan 2014-12-02 $18,051,000
8212576 Method and apparatus for self-regulated burn-in of an integrated circuit Jae-Weon Cho, Michael M. Matera, Jongheon Jeong 2012-07-03 $20,429,000
7039842 Measuring propagation delays of programmable logic devices Trent Whitten, Mose Wahlstrom 2006-05-02 $3,557,000
5517153 Power supply isolation and switching circuit Rong Yin 1996-05-14 $13,944,000