| 11495568 |
IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures |
Jayprakash Chipalkatti, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak |
2022-11-08 |
| 10943882 |
IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures |
Jayprakash Chipalkatti, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak |
2021-03-09 |
| 10219387 |
Process for manufacturing a printed circuit board having high density microvias formed in a thick substrate |
Leilei Zhang, Ronilo Boja, Abraham Yee |
2019-02-26 |
| 9760132 |
Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive pad |
Leilei Zhang, Ron Boja, Abraham Yee |
2017-09-12 |
| 9716051 |
Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarity |
Leilei Zhang, Ron Boja, Abraham Yee |
2017-07-25 |
| 9478482 |
Offset integrated circuit packaging interconnects |
Leilei Zhang |
2016-10-25 |
| 9385098 |
Variable-size solder bump structures for integrated circuit packaging |
Leilei Zhang |
2016-07-05 |
| 9368422 |
Absorbing excess under-fill flow with a solder trench |
Leilei Zhang, Ron Boja, Abraham Yee |
2016-06-14 |
| 9368439 |
Substrate build up layer to achieve both finer design rule and better package coplanarity |
Leilei Zhang |
2016-06-14 |
| 9087830 |
System, method, and computer program product for affixing a post to a substrate pad |
Leilei Zhang, Abraham Yee, Shantanu Kalchuri |
2015-07-21 |