Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11495568 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Julie Lam, Prashant Pathak | 2022-11-08 |
| 10943882 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Julie Lam, Prashant Pathak | 2021-03-09 |
| 10032692 | Semiconductor package structure | Shantanu Kalchuri, Abraham Yee | 2018-07-24 |
| 9831225 | Low-impedance power delivery for a packaged die | Gurpreet Shinh, Donald E. Templeton, Alex Waizman | 2017-11-28 |
| 9190396 | Low-impedance power delivery for a packaged die | Gurpreet Shinh, Donald E. Templeton, Alex Waizman | 2015-11-17 |
| 8951814 | Method of fabricating a flip chip semiconductor die with internal signal access | Howard Lee Marks | 2015-02-10 |
| 8357931 | Flip chip semiconductor die internal signal access system and method | Howard Lee Marks | 2013-01-22 |
| 7842948 | Flip chip semiconductor die internal signal access system and method | Howard Lee Marks | 2010-11-30 |