Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11495568 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Prashant Pathak | 2022-11-08 |
| 10943882 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Jayprakash Chipalkatti, Zuhair Bokharey, Don Templeton, Brian Schieck, Prashant Pathak | 2021-03-09 |