Issued Patents All Time
Showing 1–4 of 4 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11495568 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak | 2022-11-08 |
| 10943882 | IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures | Zuhair Bokharey, Don Templeton, Brian Schieck, Julie Lam, Prashant Pathak | 2021-03-09 |
| 10096534 | Thermal performance of logic chip in a package-on-package structure | Abraham Yee, Shantanu Kalchuri | 2018-10-09 |
| 8102038 | Semiconductor chip attach configuration having improved thermal characteristics | Kapil Heramb Sahasrabudhe | 2012-01-24 |