TL

Teh-Kuin Lee

Lsi Logic: 8 patents #212 of 1,957Top 15%
📍 San Jose, CA: #7,614 of 32,062 inventorsTop 25%
🗺 California: #73,997 of 386,348 inventorsTop 20%
Overall (All Time): #667,172 of 4,157,543Top 20%
8
Patents All Time

Issued Patents All Time

Showing 1–8 of 8 patents

Patent #TitleCo-InventorsDate
5917207 Programmable polysilicon gate array base cell architecture Michael J. Colwell, Jane C.T. Chiu, Abraham Yee, Stanley Yeh, Gobi R. Padmanabhan 1999-06-29
5812003 TTL delay matching circuit 1998-09-22
5698873 High density gate array base cell architecture Michael J. Colwell 1997-12-16
5691218 Method of fabricating a programmable polysilicon gate array base cell structure Michael J. Colwell, Jane C.T. Chiu, Abraham Yee, Stanley Yeh, Gobi R. Padmanabhan 1997-11-25
5686855 Process monitor for CMOS integrated circuits 1997-11-11
5650740 TTL delay matching circuit 1997-07-22
5631596 Process monitor for CMOS integrated circuits Nicholas Sporck 1997-05-20
5486786 Process monitor for CMOS integrated circuits 1996-01-23