Issued Patents All Time
Showing 1–5 of 5 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6432759 | Method of forming source and drain regions for CMOS devices | — | 2002-08-13 |
| 6093936 | Integrated circuit with isolation of field oxidation by noble gas implantation | Abraham Yee, Sheldon Aronowitz | 2000-07-25 |
| 5717238 | Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device | Sheldon Aronowitz, James Kimball, Gobi R. Padmanabhan, Douglas T. Grider, Chi-Yi Kao | 1998-02-10 |
| 5585286 | Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device | Sheldon Aronowitz, James Kimball, Gobi R. Padmanabhan, Douglas T. Grider, Chi-Yi Kao | 1996-12-17 |
| 5468974 | Control and modification of dopant distribution and activation in polysilicon | Sheldon Aronowitz, Yen-Hui Ku | 1995-11-21 |