GP

Gobi R. Padmanabhan

NS National Semiconductor: 22 patents #55 of 2,238Top 3%
Lsi Logic: 17 patents #73 of 1,957Top 4%
TI Texas Instruments: 1 patents #7,357 of 12,488Top 60%
📍 Sunnyvale, CA: #487 of 14,302 inventorsTop 4%
🗺 California: #11,329 of 386,348 inventorsTop 3%
Overall (All Time): #80,098 of 4,157,543Top 2%
40
Patents All Time

Issued Patents All Time

Showing 26–40 of 40 patents

Patent #TitleCo-InventorsDate
5827777 Method of making a barrier metal technology for tungsten plug interconnection Richard Schinella, Joseph M. Zelayeta 1998-10-27
5799080 Semiconductor chip having identification/encryption code Joseph M. Zelayeta, Visvamohan Yegnashankaran, James W. Hively, John Daane 1998-08-25
5796130 Non-rectangular MOS device configurations for gate array type integrated circuits Tim Carmichael, Abraham Yee, Stanley Yeh 1998-08-18
5777383 Semiconductor chip package with interconnect layers and routing and testing methods Mark Phillip Stager, Abraham Yee 1998-07-07
5776831 Method of forming a high electromigration resistant metallization system Prabhakar P. Tripathi 1998-07-07
5731223 Array of solder pads on an integrated circuit 1998-03-24
5721151 Method of fabricating a gate array integrated circuit including interconnectable macro-arrays Abraham Yee 1998-02-24
5717238 Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Douglas T. Grider, Chi-Yi Kao 1998-02-10
5702957 Method of making buried metallization structure 1997-12-30
5691218 Method of fabricating a programmable polysilicon gate array base cell structure Michael J. Colwell, Teh-Kuin Lee, Jane C.T. Chiu, Abraham Yee, Stanley Yeh 1997-11-25
5621616 High density CMOS integrated circuit with heat transfer structure for improved cooling Alexander H. Owens 1997-04-15
5600182 Barrier metal technology for tungsten plug interconnection Richard Schinella, Joseph M. Zelayeta 1997-02-04
5585286 Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device Sheldon Aronowitz, James Kimball, Yu-Lam Ho, Douglas T. Grider, Chi-Yi Kao 1996-12-17
5440154 Non-rectangular MOS device configurations for gate array type integrated circuits Tim Carmichael, Abraham Yee, Stanley Yeh 1995-08-08
5358886 Method of making integrated circuit structure with programmable conductive electrode/interconnect material Abraham Yee, Stanley Yeh, Tim Carmichael 1994-10-25