JZ

Joseph M. Zelayeta

Lsi Logic: 3 patents #574 of 1,957Top 30%
📍 Saratoga, CA: #1,541 of 2,933 inventorsTop 55%
🗺 California: #149,087 of 386,348 inventorsTop 40%
Overall (All Time): #1,640,504 of 4,157,543Top 40%
3
Patents All Time

Issued Patents All Time

Showing 1–3 of 3 patents

Patent #TitleCo-InventorsDate
5827777 Method of making a barrier metal technology for tungsten plug interconnection Richard Schinella, Gobi R. Padmanabhan 1998-10-27
5799080 Semiconductor chip having identification/encryption code Gobi R. Padmanabhan, Visvamohan Yegnashankaran, James W. Hively, John Daane 1998-08-25
5600182 Barrier metal technology for tungsten plug interconnection Richard Schinella, Gobi R. Padmanabhan 1997-02-04