Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7081296 | Method for growing thin films | Sheldon Aronowitz, Vladimir Zubkov | 2006-07-25 |
| 7020859 | Process skew results for integrated circuits | — | 2006-03-28 |
| 6881664 | Process for planarizing upper surface of damascene wiring structure for integrated circuit structures | Wilbur G. Catabay, Zhihai Wang, Wei-Jen Hsia | 2005-04-19 |
| 6800940 | Low k dielectric composite layer for integrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning | Wilbur G. Catabay | 2004-10-05 |
| 6747358 | Self-aligned alloy capping layers for copper interconnect structures | Paul Rissman, Sheldon Aronowitz, Vladimir Zubkov | 2004-06-08 |
| 6743474 | Method for growing thin films | Sheldon Aronowitz, Vladimir Zubkov | 2004-06-01 |
| 6730588 | Method of forming SiGe gate electrode | — | 2004-05-04 |
| 6673498 | Method for reticle formation utilizing metal vaporization | Sheldon Aronowitz, Vladimir Zubkov | 2004-01-06 |
| 6566262 | Method for creating self-aligned alloy capping layers for copper interconnect structures | Paul Rissman, Sheldon Aronowitz, Vladimir Zubkov | 2003-05-20 |
| 6532585 | Method and apparatus for application of proximity correction with relative segmentation | Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Nicholas F. Pasch, Mario Garza +3 more | 2003-03-11 |
| 6518193 | Substrate processing system | Kiran Kumar, Zhihai Wang, Rudy Rios, Wilbur G. Catabay | 2003-02-11 |
| 6503840 | Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning | Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar +2 more | 2003-01-07 |
| 6499003 | Method and apparatus for application of proximity correction with unitary segmentation | Edwin Jones, Dusan Petranovic, Ranko Scepanovic, Nicholas F. Pasch, Mario Garza +3 more | 2002-12-24 |
| 6426286 | Interconnection system with lateral barrier layer | Valeriy Sukharev | 2002-07-30 |
| 6391795 | Low k dielectric composite layer for intergrated circuit structure which provides void-free low k dielectric material between metal lines while mitigating via poisoning | Wilbur G. Catabay | 2002-05-21 |
| 6350700 | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure | Wilbur G. Catabay, Philippe Schoenborn | 2002-02-26 |
| 6175953 | Method and apparatus for general systematic application of proximity correction | Ranko Scepanovic, Dusan Petranovic, Edwin Jones, Nicholas F. Pasch, Mario Garza +3 more | 2001-01-16 |
| 6174630 | Method of proximity correction with relative segmentation | Dusan Petranovic, Ranko Scepanovic, Edwin Jones, Nicholas F. Pasch, Mario Garza +3 more | 2001-01-16 |
| 5895261 | Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench | Mahesh K. Sanganeria | 1999-04-20 |
| 5827777 | Method of making a barrier metal technology for tungsten plug interconnection | Gobi R. Padmanabhan, Joseph M. Zelayeta | 1998-10-27 |
| 5674774 | Method of making self-aligned remote polysilicon contacts | Nicholas F. Pasch, Ashok K. Kapoor | 1997-10-07 |
| 5670425 | Process for making integrated circuit structure comprising local area interconnects formed over semiconductor substrate by selective deposition on seed layer in patterned trench | Mahesh K. Sanganeria | 1997-09-23 |
| 5663017 | Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility | Keith K. Chao | 1997-09-02 |
| 5652163 | Use of reticle stitching to provide design flexibility | Keith K. Chao | 1997-07-29 |
| 5600182 | Barrier metal technology for tungsten plug interconnection | Gobi R. Padmanabhan, Joseph M. Zelayeta | 1997-02-04 |