Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7379836 | Method of using automated test equipment to screen for leakage inducing defects after calibration to intrinsic leakage | Ramit Bhandari, Tony Lo, Anh-Ha Tran | 2008-05-27 |
| 7071113 | Process for removal of photoresist mask used for making vias in low K carbon-doped silicon oxide dielectric material, and for removal of etch residues from formation of vias and removal of photoresist mask | Yong-Bae Kim | 2006-07-04 |
| 6969683 | Method of preventing resist poisoning in dual damascene structures | Rongxiang Hu, Yongbae Kim, Sang-Yun Lee, Hiroaki Takikawa, Shumay X. Dou +5 more | 2005-11-29 |
| 6846569 | Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication | John Hu, Ana Ley | 2005-01-25 |
| 6743725 | High selectivity SiC etch in integrated circuit fabrication | Rongxiang Hu, Masaichi Eda | 2004-06-01 |
| 6713386 | Method of preventing resist poisoning in dual damascene structures | Rongxiang Hu, Yongbae Kim, Sang-Yun Lee, Hiroaki Takikawa, Shumay X. Dou +5 more | 2004-03-30 |
| 6673721 | PROCESS FOR REMOVAL OF PHOTORESIST MASK USED FOR MAKING VIAS IN LOW K CARBON-DOPED SILICON OXIDE DIELECTRIC MATERIAL, AND FOR REMOVAL OF ETCH RESIDUES FROM FORMATION OF VIAS AND REMOVAL OF PHOTORESIST MASK | Yong-Bae Kim | 2004-01-06 |
| 6579777 | Method of forming local oxidation with sloped silicon recess | Ting-Pwu Yen, Pamela Trammel, Alexander H. Owens | 2003-06-17 |
| 6576404 | Carbon-doped hard mask and method of passivating structures during semiconductor device fabrication | John Hu, Ana Ley | 2003-06-10 |
| 6559048 | Method of making a sloped sidewall via for integrated circuit structure to suppress via poisoning | Yong-Bae Kim, Kai Zhang | 2003-05-06 |
| 6506670 | Self aligned gate | — | 2003-01-14 |
| 6503840 | Process for forming metal-filled openings in low dielectric constant dielectric material while inhibiting via poisoning | Wilbur G. Catabay, Wei-Jen Hsia, Hong-Qiang Lu, Yong-Bae Kim, Kiran Kumar +2 more | 2003-01-07 |
| 6350700 | Process for forming trenches and vias in layers of low dielectric constant carbon-doped silicon oxide dielectric material of an integrated circuit structure | Richard Schinella, Wilbur G. Catabay | 2002-02-26 |
| 6062163 | Plasma initiating assembly | Roger Patrick, Mark Franklin, Frank Bose | 2000-05-16 |
| 5902704 | Process for forming photoresist mask over integrated circuit structures with critical dimension control | John Haywood | 1999-05-11 |
| 5877530 | Formation of gradient doped profile region between channel region and heavily doped source/drain contact region of MOS device in integrated circuit structure using a re-entrant gate electrode and a higher dose drain implantation | Sheldon Aronowitz, Laique Khan | 1999-03-02 |
| 5663083 | Process for making improved MOS structure with hot carrier reduction | Sungki O | 1997-09-02 |
| 5639519 | Method for igniting low pressure inductively coupled plasma | Roger Patrick, Mark Franklin, Frank Bose | 1997-06-17 |
| 5598021 | MOS structure with hot carrier reduction | Sungki O | 1997-01-28 |
| 5578165 | Coil configurations for improved uniformity in inductively coupled plasma systems | Roger Patrick, Frank Bose, Harry Toda | 1996-11-26 |
| 5474648 | Uniform and repeatable plasma processing | Roger Patrick, Frank Bose | 1995-12-12 |
| 5468296 | Apparatus for igniting low pressure inductively coupled plasma | Roger Patrick, Mark Franklin, Frank Bose | 1995-11-21 |
| 5413966 | Shallow trench etch | — | 1995-05-09 |
| 5401350 | Coil configurations for improved uniformity in inductively coupled plasma systems | Roger Patrick, Frank Bose, Harry Toda | 1995-03-28 |
| 5362356 | Plasma etching process control | — | 1994-11-08 |