Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7407857 | Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source region | Ching-Shi Jeno | 2008-08-05 |
| 7199424 | Scalable flash EEPROM memory cell with notched floating gate and graded source region | Ching-Shi Jenq | 2007-04-03 |
| 7009244 | Scalable flash EEPROM memory cell with notched floating gate and graded source region | Ching-Shi Jenq | 2006-03-07 |
| 6900999 | Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratio | Kee Park | 2005-05-31 |
| 6579777 | Method of forming local oxidation with sloped silicon recess | Pamela Trammel, Philippe Schoenborn, Alexander H. Owens | 2003-06-17 |
| 5977638 | Edge metal for interconnect layers | T. J. Rodgers, Sam Geha, Chris Petti | 1999-11-02 |
| 5965924 | Metal plug local interconnect | — | 1999-10-12 |
| 5861676 | Method of forming robust interconnect and contact structures in a semiconductor and/or integrated circuit | — | 1999-01-19 |
| 5656861 | Self-aligning contact and interconnect structure | Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1997-08-12 |
| 5620919 | Methods for fabricating integrated circuits including openings to transistor regions | Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1997-04-15 |
| 5483104 | Self-aligning contact and interconnect structure | Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1996-01-09 |
| 5477074 | Semiconductor structure using local planarization with self-aligned transistors | — | 1995-12-19 |
| 5465004 | Programmable semiconductor integrated circuits having fusible links | Sheldon C. P. Lim, Julie W. Hellstrom | 1995-11-07 |
| 5348897 | Transistor fabrication methods using overlapping masks | — | 1994-09-20 |
| 5340774 | Semiconductor fabrication technique using local planarization with self-aligned transistors | — | 1994-08-23 |
| 5172211 | High resistance Polysilicon load resistor | Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1992-12-15 |
| 5168076 | Method of fabricating a high resistance polysilicon load resistor | Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1992-12-01 |
| 5166771 | Self-aligning contact and interconnect structure | Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1992-11-24 |
| 5124774 | Compact SRAM cell layout | Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more | 1992-06-23 |
| 5015604 | Fabrication method using oxidation to control size of fusible link | Sheldon C. P. Lim, Julie W. Hellstrom | 1991-05-14 |