Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8765534 | Method for improved mobility using hybrid orientation technology (HOT) in conjunction with selective epitaxy and related apparatus | — | 2014-07-01 |
| 8395216 | Method for using hybrid orientation technology (HOT) in conjunction with selective epitaxy to form semiconductor devices with regions of different electron and hole mobilities and related apparatus | — | 2013-03-12 |
| 7795126 | Electrical die contact structure and fabrication method | Ashok S. Prabhu, Sadanand R. Patil, Shaw Wei Lee | 2010-09-14 |
| 7340181 | Electrical die contact structure and fabrication method | Ashok S. Prabhu, Sadanand R. Patil, Shaw Wei Lee | 2008-03-04 |
| 6946706 | LDMOS transistor structure for improving hot carrier reliability | Douglas Brisbin, David Tsuei, Andy Strachan | 2005-09-20 |
| 6586302 | Method of using trenching techniques to make a transistor with a floating gate | Peter J. Hopper, Yuri Mirgorodski, Chin-Miin Shyu, David Tsuei, Peter Johnson | 2003-07-01 |
| 6579777 | Method of forming local oxidation with sloped silicon recess | Ting-Pwu Yen, Pamela Trammel, Philippe Schoenborn | 2003-06-17 |
| 5998280 | Modified recessed locos isolation process for deep sub-micron device processes | Albert Bergemont | 1999-12-07 |
| 5661069 | Method of forming an MOS-type integrated circuit structure with a diode formed in the substrate under a polysilicon gate electrode to conserve space | Shahin Toutounchi | 1997-08-26 |
| 5621616 | High density CMOS integrated circuit with heat transfer structure for improved cooling | Gobi R. Padmanabhan | 1997-04-15 |
| 5612552 | Multilevel gate array integrated circuit structure with perpendicular access to all active device regions | — | 1997-03-18 |
| 5561319 | Integrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereof | Shahin Toutounchi, Abraham Yee, Michael LYU | 1996-10-01 |
| 5516731 | High-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistance | Shahin Toutounchi, Abraham Yee, Michael LYU | 1996-05-14 |
| 5220192 | Radiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereof | Mike Lyu, Shahin Toutounchi, Abraham Yee | 1993-06-15 |
| 5091321 | Method for making an NPN transistor with controlled base width compatible with making a Bi-MOS integrated circuit | Wing K. Huie | 1992-02-25 |
| 5045492 | Method of making integrated circuit with high current transistor and CMOS transistors | Wing K. Huie, David S. Pan | 1991-09-03 |
| 4914051 | Method for making a vertical power DMOS transistor with small signal bipolar transistors | Wing K. Huie, David S. Pan, Michael J. Zunino | 1990-04-03 |
| 4774202 | Memory device with interconnected polysilicon layers and method for making | David S. Pan, Kanak C. Sarma, Mark A. Halfacre, Brian K. Rosier | 1988-09-27 |
| 4706102 | Memory device with interconnected polysilicon layers and method for making | David S. Pan, Kanak C. Sarma, Mark A. Halfacre, Brian K. Rosier | 1987-11-10 |
| 4646425 | Method for making a self-aligned CMOS EPROM wherein the EPROM floating gate and CMOS gates are made from one polysilicon layer | Mark A. Halfacre, David S. Pan | 1987-03-03 |
| 4598460 | Method of making a CMOS EPROM with independently selectable thresholds | Mark A. Halfacre, David S. Pan | 1986-07-08 |
| 4590665 | Method for double doping sources and drains in an EPROM | Mark A. Halfacre, Wing K. Huie, David S. Pan | 1986-05-27 |