Issued Patents All Time
Showing 1–25 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8669157 | Non-volatile memory cell having a heating element and a substrate-based control gate | Jeffrey A. Babcock, Natalia Lavrovskaya, Saurabh Desai | 2014-03-11 |
| 8554529 | Black box model for large signal transient integrated circuit simulation | Peter J. Hopper, William French, Philipp Lindorfer | 2013-10-08 |
| 8453494 | Gas detector that utilizes an electric field to assist in the collection and removal of gas molecules | Jeffrey A. Babcock, Peter J. Hopper | 2013-06-04 |
| 8247862 | Method of enhancing charge storage in an E2PROM cell | Jeff Babcock, Natalia Lavrovskaya, Saurabh Desai | 2012-08-21 |
| 8207578 | Method of forming a region of graded doping concentration in a semiconductor device and related apparatus | William French, Erika Lynn Mazotti | 2012-06-26 |
| 8183621 | Non-volatile memory cell having a heating element and a substrate-based control gate | Jeffrey A. Babcock, Natalia Lavrovskaya, Saurabh Desai | 2012-05-22 |
| 7978519 | Method of reading an NVM cell that utilizes a gated diode | Peter J. Hopper, Roozbeh Parsa | 2011-07-12 |
| 7969790 | Method of erasing an NVM cell that utilizes a gated diode | Peter J. Hopper, Roozbeh Parsa | 2011-06-28 |
| 7964485 | Method of forming a region of graded doping concentration in a semiconductor device and related apparatus | William French, Erika Lynn Mazotti | 2011-06-21 |
| 7919807 | Non-volatile memory cell with heating element | Jeffrey A. Babcock, Natalia Lavrovskaya, Saurabh Desai | 2011-04-05 |
| 7919805 | Non-volatile memory cell with two capacitors and one PNP transistor and a method of forming such a cell in a 1-poly SOI technology | Natalia Lavrovskaya, Saurabh Desai | 2011-04-05 |
| 7911869 | Fuse-type memory cells based on irreversible snapback device | Vladislav Vashchenko, Peter J. Hopper | 2011-03-22 |
| 7859912 | Mid-size NVM cell and array utilizing gated diode for low current programming | Peter J. Hopper, Roozbeh Parsa | 2010-12-28 |
| 7808034 | Non-volatile memory cell with fully isolated substrate as charge storage | Jeff Babcock, Natasha Layrovskava, Saurahh Desai | 2010-10-05 |
| 7719048 | Heating element for enhanced E2PROM | Jeff Babcock, Natalia Lavrovskaya, Saurabh Desai | 2010-05-18 |
| 7705403 | Programmable ESD protection structure | Vladislav Vashchenko, Peter J. Hopper | 2010-04-27 |
| 7663173 | Non-volatile memory cell with poly filled trench as control gate and fully isolated substrate as charge storage | Saurabh Desai, Natasha Lavrovskaya, Jeff Babcock | 2010-02-16 |
| 7651913 | Method of forming non-volatile memory (NVM) retention improvement utilizing protective electrical shield | Peter J. Hopper, Vladislav Vashchenko | 2010-01-26 |
| 7651897 | Integrated circuit with metal heat flow path coupled to transistor and method for manufacturing such circuit | Vladislav Vashchenko, Peter J. Hopper | 2010-01-26 |
| 7435628 | Method of forming a vertical MOS transistor | Peter J. Hopper, Vladislav Vashchenko, Peter Johnson | 2008-10-14 |
| 7425741 | EEPROM structure with improved data retention utilizing biased metal plate and conductive layer exclusion | Andrew Strachan, Natalia Lavrovskaya, Saurabh Desai, Roozbeh Parsa | 2008-09-16 |
| 7422952 | Method of forming a BJT with ESD self protection | Vladislav Vashchenko, Peter J. Hopper | 2008-09-09 |
| 7375393 | Non-volatile memory (NVM) retention improvement utilizing protective electrical shield | Peter J. Hopper, Vladislav Vashchenko | 2008-05-20 |
| 7339835 | Non-volatile memory structure and erase method with floating gate voltage control | Peter J. Hopper, Vladislav Vashchenko | 2008-03-04 |
| 7298599 | Multistage snapback ESD protection network | Vladislav Vashchenko, Peter J. Hopper, Philip Lindorpher | 2007-11-20 |