Issued Patents All Time
Showing 25 most recent of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8311762 | Manufacturing test for a programmable integrated circuit implementing a specific user design | Ismed D. Hartanto, Andrew M. Taylor | 2012-11-13 |
| 7947980 | Non-volatile memory cell with charge storage element and method of programming | James Karp, Jeongheon Jeong, Michael G. Ahrens, Michael J. Hart | 2011-05-24 |
| 7917820 | Testing an embedded core | Adarsh Pavle | 2011-03-29 |
| 7761755 | Circuit for and method of testing for faults in a programmable logic device | Tassanee Payakapan, Ismed D. Hartanto | 2010-07-20 |
| 7725787 | Testing of a programmable device | Robert W. Wells, Shekhar Bapat, Tassanee Payakapan | 2010-05-25 |
| 7687797 | Three-terminal non-volatile memory element with hybrid gate dielectric | James Karp, Daniel Gitlin, Michael G. Ahrens, Jongheon Jeong | 2010-03-30 |
| 7544968 | Non-volatile memory cell with charge storage element and method of programming | James Karp, Jongheon Jeong, Michael G. Ahrens, Michael J. Hart | 2009-06-09 |
| 7452765 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Michael J. Hart +3 more | 2008-11-18 |
| 7454675 | Testing of a programmable device | Robert W. Wells, Shekhar Bapat, Tassanee Payakapan | 2008-11-18 |
| 7450431 | PMOS three-terminal non-volatile memory element and method of programming | James Karp, Jongheon Jeong, Michael G. Ahrens | 2008-11-11 |
| 7420842 | Method of programming a three-terminal non-volatile memory element using source-drain bias | Michael G. Ahrens, James Karp, Jongheon Jeong | 2008-09-02 |
| 7302625 | Built-in self test (BIST) technology for testing field programmable gate arrays (FPGAs) using partial reconfiguration | Tassanee Payakapan, Lee N. Chung | 2007-11-27 |
| 7219287 | Automated fault diagnosis in a programmable device | Andrew M. Taylor | 2007-05-15 |
| 6982451 | Single event upset in SRAM cells in FPGAs with high resistivity gate structures | Martin L. Voogel, Austin H. Lesea, Joseph J. Fabula, Carl H. Carmichael, Michael J. Hart +3 more | 2006-01-03 |
| 6920621 | Methods of testing for shorts in programmable logic devices using relative quiescent current measurements | Erik Vaclav Chmelar, Robert W. Wells | 2005-07-19 |
| 6891395 | Application-specific testing methods for programmable logic devices | Robert W. Wells, Zhi-Min Ling, Robert D. Patrie, Vincent L. Tong, Jae-Weon Cho | 2005-05-10 |
| 6817006 | Application-specific testing methods for programmable logic devices | Robert W. Wells, Zhi-Min Ling, Robert D. Patrie, Vincent L. Tong, Jae-Weon Cho | 2004-11-09 |
| 6732309 | Method for testing faults in a programmable logic device | Andrew W. Lai | 2004-05-04 |
| 6732348 | Method for locating faults in a programmable logic device | Mehdi Baradaran Tahoori | 2004-05-04 |
| 6645802 | Method of forming a zener diode | Sheau-Suey Li, Michael J. Hart, Xin Wu, Daniel Gitlin | 2003-11-11 |
| 6594610 | Fault emulation testing of programmable logic devices | Anthony P. Calderone, Zhi-Min Ling, Robert D. Patrie, Eric J. Thorne, Robert W. Wells | 2003-07-15 |
| 6549458 | Non-volatile memory array using gate breakdown structures | Kameswara K. Rao, Martin L. Voogel, James Karp, Michael J. Hart, Daniel Gitlin +3 more | 2003-04-15 |
| 6522582 | Non-volatile memory array using gate breakdown structures | Kameswara K. Rao, Martin L. Voogel, James Karp, Michael J. Hart, Daniel Gitlin +3 more | 2003-02-18 |
| 6268639 | Electrostatic-discharge protection circuit | Sheau-Suey Li, Michael J. Hart, Xin Wu, Daniel Gitlin | 2001-07-31 |
| 6266269 | Three terminal non-volatile memory element | James Karp, Daniel Gitlin | 2001-07-24 |