Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
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Kameswara K. Rao — 38 Patents

AMD: 30 patents #323 of 9,280Top 4%
MOMosys: 2 patents #22 of 45Top 50%
SISignetics: 2 patents #22 of 93Top 25%
CSCatalyst Semiconductor: 1 patents #21 of 41Top 55%
Intel: 1 patents #18,326 of 30,777Top 60%
Santa Clara, CA: #341 of 9,301 inventorsTop 4%
California: #12,412 of 386,348 inventorsTop 4%
Overall (All Time): #84,675 of 4,157,543Top 3%
38 Patents All Time
Kameswara K. Rao has been granted 38 US patents while listed as an inventor at AMD. The first was granted in 1986 and the most recent in April 2012. Kameswara K. Rao ranks #84,675 of 4,157,543 US inventors in our database (top 2.0%). Patent records list Kameswara K. Rao in Santa Clara, CA, US.

Patents per Year

Patents granted per year, 1986 to 2012Bar chart with a peak of 5 patents in 1999.peak 51986: 2 patents19861987: 1 patents1990: 1 patents19901993: 1 patents1996: 1 patents19961997: 2 patents1998: 4 patents19981999: 5 patents2000: 2 patents20002001: 4 patents2002: 2 patents20022003: 2 patents2005: 1 patents20052006: 3 patents2009: 4 patents20092011: 1 patents2012: 2 patents2012

Issued Patents All Time

Showing 1–25 of 38 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
8161355 Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee Tee Chua +1 more 2012-04-17 $2,195,000
8099691 Disabling unused/inactive resources in an integrated circuit for static power reduction Tim Tuan, Robert O. Conn 2012-01-17 $8,414,000
8081521 Two bits per cell non-volatile memory architecture Chee Tee Chua, Vithal Rao, Jawji Chen, Da-Guang Yu, J. Eric Ruetz +1 more 2011-12-20 $1,305,000
7581124 Method and mechanism for controlling power consumption of an integrated circuit Neil G. Jacobson, Matthew T. Murphy, Tim Tuan, Robert O. Conn 2009-08-25 $24,447,000
7562332 Disabling unused/inactive resources in programmable logic devices for static power reduction Tim Tuan, Robert O. Conn 2009-07-14 $44,186,000
7549139 Tuning programmable logic devices for low-power design implementation Tim Tuan, Jan L. deJong, Robert O. Conn 2009-06-16 $23,060,000
7504854 Regulating unused/inactive resources in programmable logic devices for static power reduction Kevin T. Look, Michael J. Hart, Tim Tuan, Robert O. Conn 2009-03-17 $3,565,000
7117373 Bitstream for configuring a PLD with encrypted design data Stephen M. Trimberger, Raymond C. Pang, Walter N. Sze, Jennifer Wong 2006-10-03 $7,381,000
7098689 Disabling unused/inactive resources in programmable logic devices for static power reduction Tim Tuan, Robert O. Conn 2006-08-29 $7,450,000
7046071 Series capacitor coupling multiplexer for programmable logic devices Robert O. Conn 2006-05-16 $5,099,000
6931543 Programmable logic device with decryption algorithm and decryption key Raymond C. Pang, Walter N. Sze, Jennifer Wong, Stephen M. Trimberger, John M. Thendean 2005-08-16 $21,145,000
6549458 Non-volatile memory array using gate breakdown structures Martin L. Voogel, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin +3 more 2003-04-15 $62,996,000
6522582 Non-volatile memory array using gate breakdown structures Martin L. Voogel, James Karp, Shahin Toutounchi, Michael J. Hart, Daniel Gitlin +3 more 2003-02-18 $55,787,000
6438065 Redundancy architecture and method for non-volatile storage Martin L. Voogel, Michael J. Hart 2002-08-20 $13,062,000
6366117 Nonvolatile/battery-backed key in PLD Raymond C. Pang, Jennifer Wong, Scott O. Frake, Jane W. Sowards, Venu M. Kondapalli +2 more 2002-04-02 $73,316,000
6265266 Method of forming a two transistor flash EPROM cell Anders T. Dejenfelt, George H. Simmons, Tomoyuki Furuhata 2001-07-24 $118,810,000
6243294 Memory architecture for non-volatile storage using gate breakdown structure in standard sub 0.35 micron process Martin L. Voogel, Michael J. Hart 2001-06-05 $72,709,000
6208549 One-time programmable poly-fuse circuit for implementing non-volatile functions in a standard sub 0.35 micron CMOS Martin L. Voogel 2001-03-27 $124,669,000
6177830 High voltage charge pump using standard sub 0.35 micron CMOS process 2001-01-23 $164,447,000
6055205 Decoder for a non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process Martin L. Voogel 2000-04-25 $165,779,000
6044012 Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process Martin L. Voogel, Shahin Toutounchi, James Karp 2000-03-28 $131,220,000
5991880 Overridable data protection mechanism for PLDs Derek R. Curd, Neil G. Jacobson, Sholeh Diba, Napoleon W. Lee, Wei-Yi Ku 1999-11-23 $39,764,000
5959885 Non-volatile memory array using single poly EEPROM in standard CMOS process 1999-09-28 $36,363,000
5949712 Non-volatile memory array using gate breakdown structure Martin L. Voogel 1999-09-07 $38,555,000
5949987 Efficient in-system programming structure and method for non-volatile programmable logic devices Derek R. Curd, Napoleon W. Lee 1999-09-07 $38,555,000