Jawji Chen — 6 Patents at Integrated Memory Logic

Jawji Chen has been granted 6 US patents while listed as an inventor at Integrated Memory Logic. The first was granted in 2000 and the most recent in April 2012. Jawji Chen ranks #779,687 of 4,157,543 US inventors in our database (top 18.8%). Patent records list Jawji Chen in Fremont, CA, US.

Issued Patents All Time

Showing 1–6 of 6 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
8161355	Automatic refresh for improving data retention and endurance characteristics of an embedded non-volatile memory in a standard CMOS logic process	Stephen Fung, Vithal Rao, Da-Guang Yu, J. Eric Ruetz, Chee Tee Chua +1 more	2012-04-17	$2,195,000
8081521	Two bits per cell non-volatile memory architecture	Chee Tee Chua, Kameswara K. Rao, Vithal Rao, Da-Guang Yu, J. Eric Ruetz +1 more	2011-12-20	$1,305,000
6477592	System for I/O interfacing for semiconductor chip utilizing addition of reference element to each data element in first data stream and interpret to recover data elements of second data stream	Shuen-Chin Chang, Yong-Eun Park, Cindy NG, Chiayao S. Tung, Jeongsik Yang	2002-11-05
6324602	Advanced input/output interface for an integrated circuit device using two-level to multi-level signal conversion	Shuen-Chin Chang, Yong-Eun Park	2001-11-27
6259634	Pseudo dual-port DRAM for simultaneous read/write access	Subramani Kengeri	2001-07-10
6076132	Arbitration method and circuit to increase access without increasing latency	—	2000-06-13

Jawji Chen — 6 Patents

Issued Patents All Time

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