| 6466049 |
Clock enable control circuit for flip flops |
Sholeh Diba, Jeffrey H. Seltzer |
2002-10-15 |
| 5991880 |
Overridable data protection mechanism for PLDs |
Derek R. Curd, Neil G. Jacobson, Sholeh Diba, Napoleon W. Lee, Kameswara K. Rao |
1999-11-23 |
| 5838901 |
Overridable data protection mechanism for PLDs |
Derek R. Curd, Neil G. Jacobson, Sholeh Diba, Napoleon W. Lee, Kameswara K. Rao |
1998-11-17 |
| 5670896 |
High speed product term assignment for output enable, clock, inversion and set/reset in a programmable logic device |
Sholeh Diba |
1997-09-23 |
| 5631583 |
Sense amplifier for programmable logic device having selectable power modes |
Napoleon W. Lee |
1997-05-20 |
| 5617041 |
Method and apparatus for reducing coupling switching noise in interconnect array matrix |
Napoleon W. Lee, Hy V. Nguyen, Sholeh Diba |
1997-04-01 |
| 5610536 |
Macrocell architecture with high speed product terms |
Sholeh Diba |
1997-03-11 |
| 5563827 |
Wordline driver for flash PLD |
Napoleon W. Lee, Derek R. Curd, Sholeh Diba, George H. Simmons |
1996-10-08 |
| 5530384 |
Sense amplifier having selectable power and speed modes |
Napoleon W. Lee |
1996-06-25 |
| 5361229 |
Precharging bitlines for robust reading of latch data |
David Chiang |
1994-11-01 |
| 5349249 |
Programmable logic device having security elements located amongst configuration bit location to prevent unauthorized reading |
David Chiang, Thomas Y. Ho, George H. Simmons, Robert W. Barker, II |
1994-09-20 |