Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
DC

Derek R. Curd — 26 Patents

AMD: 23 patents #473 of 9,280Top 6%
San Jose, CA: #2,428 of 32,062 inventorsTop 8%
California: #20,975 of 386,348 inventorsTop 6%
Overall (All Time): #150,017 of 4,157,543Top 4%
26 Patents All Time
Derek R. Curd has been granted 26 US patents while listed as an inventor at AMD. The first was granted in 1996 and the most recent in June 2007. Derek R. Curd ranks #150,017 of 4,157,543 US inventors in our database (top 3.6%). Patent records list Derek R. Curd in San Jose, CA, US.

Issued Patents All Time

Showing 1–25 of 26 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7227378 Reconfiguration of a programmable logic device using internal control Brandon J. Blodget, Scott P. McMillan, Philip B. James-Roxby, Prasanna Sundararajan, Eric R. Keller +3 more 2007-06-05 $7,795,000
7143329 FPGA configuration memory with built-in error correction mechanism Stephen M. Trimberger, Austin H. Lesea 2006-11-28 $3,263,000
6920627 Reconfiguration of a programmable logic device using internal control Brandon J. Blodget, Scott P. McMillan, Philip B. James-Roxby, Prasanna Sundararajan, Eric R. Keller +3 more 2005-07-19 $20,753,000
6907595 Partial reconfiguration of a programmable logic device using an on-chip processor Punit S. Kalra, Richard J. LeBlanc, Vincent P. Eck, Stephen W. Trynosky, Jeffrey V. Lindholm +1 more 2005-06-14 $16,208,000
6549016 Negative voltage detector Fariba Farahanchi 2003-04-15 $62,996,000
6353333 Simplified 5V tolerance circuit for 3.3V I/O design Hy V. Nguyen 2002-03-05 $33,317,000
6314539 Boundary-scan register cell with bypass circuit Neil G. Jacobson 2001-11-06 $223,128,000
6278327 Negative voltage detector Fariba Farahanchi 2001-08-21 $78,252,000
6172518 Method of minimizing power use in programmable logic devices Jesse H. Jenkins, IV., Jeffrey H. Seltzer 2001-01-09 $77,634,000
6121795 Low-voltage input/output circuit with high voltage tolerance Hy V. Nguyen 2000-09-19 $141,830,000
5991880 Overridable data protection mechanism for PLDs Neil G. Jacobson, Sholeh Diba, Napoleon W. Lee, Wei-Yi Ku, Kameswara K. Rao 1999-11-23 $39,764,000
5949987 Efficient in-system programming structure and method for non-volatile programmable logic devices Kameswara K. Rao, Napoleon W. Lee 1999-09-07 $38,555,000
5898618 Enhanced blank check erase verify reference voltage source Shankar Lakkapragada 1999-04-27 $20,208,000
5889701 Method and apparatus for selecting optimum levels for in-system programmable charge pumps Sunae Kang, Rafael San Luis, Ronald J. Mack 1999-03-30 $27,659,000
5841867 On-chip programming verification system for PLDs Neil G. Jacobson 1998-11-24 $25,954,000
5838901 Overridable data protection mechanism for PLDs Neil G. Jacobson, Sholeh Diba, Napoleon W. Lee, Wei-Yi Ku, Kameswara K. Rao 1998-11-17 $17,149,000
5831845 Voltage regulator with charge pump and parallel reference nodes Shi-dong Zhou 1998-11-03 $11,550,000
5801548 Configurable performance-optimized programmable logic device Napoleon W. Lee 1998-09-01
5764076 Circuit for partially reprogramming an operational programmable logic device Napoleon W. Lee, Jeffrey H. Seltzer, Jeffrey Goldberg, David Chiang, Kameswara K. Rao +1 more 1998-06-09 $11,764,000
5734868 Efficient in-system programming structure and method for non-volatile programmable logic devices Kameswara K. Rao, Napoleon W. Lee 1998-03-31
5689516 Reset circuit for a programmable logic device Ronald J. Mack, Sholeh Diba, Napoleon W. Lee, Kameswara K. Rao, Mihai G. Statovici 1997-11-18 $16,177,000
5661685 Programmable logic device with configurable power supply Napoleon W. Lee, Sholeh Diba, Prasad L. Sastry, Mihai G. Statovici, Kameswara K. Rao 1997-08-26 $22,418,000
5650672 High-voltage power multiplexor 1997-07-22
5563827 Wordline driver for flash PLD Napoleon W. Lee, Wei-Yi Ku, Sholeh Diba, George H. Simmons 1996-10-08 $11,438,000
5561629 Latching sense amplifier for a programmable logic device 1996-10-01 $14,129,000