Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10970446 | Automated pipeline insertion on a bus | Khang K. Dao, Sabyasachi Das | 2021-04-06 |
| 10819680 | Interface firewall for an integrated circuit of an expansion card | Sonal Santan, Umang Parekh, Khang K. Dao, Kyle Corbett | 2020-10-27 |
| 8769449 | System level circuit design | Adam P. Donlin, Biping Wu, Kyle Corbett, Nabeel Shirazi, Shay Ping Seng +4 more | 2014-07-01 |
| 7970977 | Deadlock-resistant bus bridge with pipeline-restricted address ranges | Kam-Wing Li, Ahmad R. Ansari, Sanford L. Helton, Tomai Knopp, Khang K. Dao | 2011-06-28 |
| 6980030 | Embedded function units with decoding | Frank C. Wirtz, II, John Hubbard, Schuyler E. Shimanek | 2005-12-27 |
| 6466049 | Clock enable control circuit for flip flops | Sholeh Diba, Wei-Yi Ku | 2002-10-15 |
| 6172518 | Method of minimizing power use in programmable logic devices | Jesse H. Jenkins, IV., Derek R. Curd | 2001-01-09 |
| 5991523 | Method and system for HDL global signal simulation and verification | Anthony D. Williams, Carol Fields, Roberta E. Fulton, Dhimant Jasubhai Patel, Veena N. Kumar | 1999-11-23 |
| 5969539 | Product term exporting mechanism and method improvement in an EPLD having high speed product term allocation structure | Isaak Veytsman, Hua Xue | 1999-10-19 |
| 5821774 | Structure and method for arithmetic function implementation in an EPLD having high speed product term allocation structure | Isaak Veytsman | 1998-10-13 |
| 5764076 | Circuit for partially reprogramming an operational programmable logic device | Napoleon W. Lee, Derek R. Curd, Jeffrey Goldberg, David Chiang, Kameswara K. Rao +1 more | 1998-06-09 |
| 5565792 | Macrocell with product-term cascade and improved flip flop utilization | David Chiang, Napoleon W. Lee, Thomas Y. Ho, David Harrison, Nicholas Kucharewski | 1996-10-15 |
| 5563529 | High speed product term allocation structure supporting logic iteration after committing device pin locations | Jesse H. Jenkins, IV, Sholeh Diba | 1996-10-08 |
| 5357153 | Macrocell with product-term cascade and improved flip flop utilization | David Chiang, Napoleon W. Lee, Thomas Y. Ho, David Harrison, Nicholas Kucharewski | 1994-10-18 |
| 5302866 | Input circuit block and method for PLDs with register clock enable selection | David Chiang, Thomas Y. Ho, Jeffrey Goldberg | 1994-04-12 |
| 4833651 | High-speed, asynchronous, No-Fall-Through, first-in-first out memory with high data integrity | Hassan Hanjani | 1989-05-23 |