| 12401364 |
Multiple partitions in a data processing array |
Juan J. Noguera Serra, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman +3 more |
2025-08-26 |
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| 12164451 |
Data processing array interface having interface tiles with multiple direct memory access circuits |
David Clarke, Peter McColgan, Juan J. Noguera Serra, Saurabh Mathur, Amarnath Kasibhatla +3 more |
2024-12-10 |
|
| 12001367 |
Multi-die integrated circuit with data processing engine array |
Juan J. Noguera Serra, Sridhar Subramanian |
2024-06-04 |
|
| 11972132 |
Data processing engine arrangement in a device |
Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more |
2024-04-30 |
|
| 11848670 |
Multiple partitions in a data processing array |
Juan J. Noguera Serra, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman +3 more |
2023-12-19 |
|
| 11693808 |
Multi-die integrated circuit with data processing engine array |
Juan J. Noguera Serra, Sridhar Subramanian |
2023-07-04 |
|
| 11669464 |
Multi-addressing mode for DMA and non-sequential read and write patterns |
Goran H K Bilski, Baris Ozgul, David Clarke, Juan J. Noguera Serra, Jan Langer +2 more |
2023-06-06 |
|
| 11520717 |
Memory tiles in data processing engine array |
David Clarke, Peter McColgan, Zachary Blaise Dickman, Jose Marques, Juan J. Noguera Serra +2 more |
2022-12-06 |
|
| 11443091 |
Data processing engines with cascade connected cores |
Peter McColgan, Baris Ozgul, David Clarke, Juan J. Noguera Serra, Goran Bilski +4 more |
2022-09-13 |
|
| 11386020 |
Programmable device having a data processing engine (DPE) array |
Matthew H. Klein, Goran H K Bilski, Juan J. Noguera Serra, Ismed D. Hartanto, Sridhar Subramanian |
2022-07-12 |
|
| 11336287 |
Data processing engine array architecture with memory tiles |
Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Peter McColgan +2 more |
2022-05-17 |
|
| 11323391 |
Multi-port stream switch for stream interconnect network |
Peter McColgan, David Clarke, Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul +1 more |
2022-05-03 |
|
| 11288222 |
Multi-die integrated circuit with data processing engine array |
Juan J. Noguera Serra, Sridhar Subramanian |
2022-03-29 |
|
| 11223351 |
Activity-aware clock gating for switches |
Amarnath Kasibhatla, Saurabh Mathur, Mansi Shrikant Patwardhan |
2022-01-11 |
$194,948,000 |
| 10866753 |
Data processing engine arrangement in a device |
Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more |
2020-12-15 |
$77,795,000 |
| 10747531 |
Core for a data processing engine in an integrated circuit |
Jan Langer, Baris Ozgul, Juan J. Noguera Serra, Goran H K Bilski |
2020-08-18 |
$22,481,000 |
| 10635622 |
System-on-chip interface architecture |
Goran H K Bilski, Juan J. Noguera Serra, David Clarke, Peter McColgan, Zachary Blaise Dickman +2 more |
2020-04-28 |
$32,103,000 |
| 9444497 |
Method and apparatus for adaptively tuning an integrated circuit |
Sundararajarao Mohan |
2016-09-13 |
$31,450,000 |
| 9355690 |
Time-multiplexed, asynchronous device |
— |
2016-05-31 |
$11,154,000 |
| 9348959 |
Optimizing supply voltage and threshold voltage |
— |
2016-05-24 |
$14,349,000 |
| 9015023 |
Device specific configuration of operating voltage |
Daniel Chung, Ronald L. Cline, Andy DeBaets, Matthew H. Klein |
2015-04-21 |
$9,984,000 |
| 8443344 |
Methods for identifying gating opportunities from a high-level language program and generating a hardware definition |
Prasanna Sundararajan |
2013-05-14 |
$4,138,000 |
| 8411527 |
Multiple sleep mode memory device |
— |
2013-04-02 |
$5,127,000 |
| 8159263 |
Programmable integrated circuit with voltage domains |
Ronald L. Cline, Arifur Rahman |
2012-04-17 |
$6,069,000 |
| 8155907 |
Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product |
Austin H. Lesea, Stephen M. Trimberger, Christopher H. Kingsley, Satyaki Das |
2012-04-10 |
$9,251,000 |
