Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8146045 | High-level circuit architecture optimizer | — | 2012-03-27 |
| 8130027 | Apparatus and method for the detection and compensation of integrated circuit performance variation | — | 2012-03-06 |
| 8099691 | Disabling unused/inactive resources in an integrated circuit for static power reduction | Kameswara K. Rao, Robert O. Conn | 2012-01-17 |
| 7992020 | Power management with packaged multi-die integrated circuit | Kerry M. Pierce, Albert Franceschino | 2011-08-02 |
| 7973556 | System and method for using reconfiguration ports for power management in integrated circuits | Juan J. Noguera Serra | 2011-07-05 |
| 7810058 | Early power estimator for integrated circuits | — | 2010-10-05 |
| 7764081 | Programmable logic device (PLD) with memory refresh based on single event upset (SEU) occurrence to maintain soft error immunity | Prasanna Sundararajan | 2010-07-27 |
| 7620926 | Methods and structures for flexible power management in integrated circuits | — | 2009-11-17 |
| 7581124 | Method and mechanism for controlling power consumption of an integrated circuit | Neil G. Jacobson, Matthew T. Murphy, Kameswara K. Rao, Robert O. Conn | 2009-08-25 |
| 7562332 | Disabling unused/inactive resources in programmable logic devices for static power reduction | Kameswara K. Rao, Robert O. Conn | 2009-07-14 |
| 7549139 | Tuning programmable logic devices for low-power design implementation | Jan L. deJong, Kameswara K. Rao, Robert O. Conn | 2009-06-16 |
| 7545177 | Method and apparatus for leakage current reduction | Sean W. Kao, Arifur Rahman | 2009-06-09 |
| 7504854 | Regulating unused/inactive resources in programmable logic devices for static power reduction | Kevin T. Look, Michael J. Hart, Kameswara K. Rao, Robert O. Conn | 2009-03-17 |
| 7498836 | Programmable low power modes for embedded memory blocks | — | 2009-03-03 |
| 7498835 | Implementation of low power standby modes for integrated circuits | Arifur Rahman, Sean W. Kao, Patrick J. Crotty, Jinsong Huang | 2009-03-03 |
| 7490302 | Power gating various number of resources based on utilization levels | Arifur Rahman, Sean W. Kao, Sathaki Das | 2009-02-10 |
| 7477073 | Structures and methods for heterogeneous low power programmable logic device | Arifur Rahman, Satyaki Das, Sean W. Kao | 2009-01-13 |
| 7417454 | Low-swing interconnections for field programmable gate arrays | Arifur Rahman, Sean W. Kao | 2008-08-26 |
| 7253661 | Method and apparatus for a configurable latch | Sean W. Kao | 2007-08-07 |
| 7243312 | Method and apparatus for power optimization during an integrated circuit design process | Patrick Lysaght, Goran Bilski | 2007-07-10 |
| 7212462 | Structure and method for suppressing sub-threshold leakage in integrated circuits | — | 2007-05-01 |
| 7098689 | Disabling unused/inactive resources in programmable logic devices for static power reduction | Kameswara K. Rao, Robert O. Conn | 2006-08-29 |
| 6950998 | Place-and-route with power analysis | — | 2005-09-27 |