Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11443091 | Data processing engines with cascade connected cores | Peter McColgan, Baris Ozgul, David Clarke, Tim Tuan, Juan J. Noguera Serra +4 more | 2022-09-13 |
| 7676661 | Method and system for function acceleration using custom instructions | Sundararajarao Mohan, Satish R. Ganesan | 2010-03-09 |
| 7490227 | Method and system to recreate instruction and data traces in an embedded processor | Jorge Ernesto Carrillo, Usha Prabhu, Navaneethan Sundaramoorthy | 2009-02-10 |
| 7426583 | Method and circuit for decoding an address of an address space | Paulo L. Dutra, Jorge Ernesto Carrillo | 2008-09-16 |
| 7380106 | Method and system for transferring data between a register in a processor and a point-to-point communication link | — | 2008-05-27 |
| 7340585 | Method and system for fast linked processor in a system on a chip (SoC) | Satish R. Ganesan, Usha Prabhu, Ralph D. Wittig | 2008-03-04 |
| 7243312 | Method and apparatus for power optimization during an integrated circuit design process | Patrick Lysaght, Tim Tuan | 2007-07-10 |
| 7181718 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Ralph D. Wittig, Jennifer Wong, David B. Squires | 2007-02-20 |
| 7131091 | Generating fast logic simulation models for a PLD design description | Satish R. Ganesan, Usha Prabhu, Paulo L. Dutra | 2006-10-31 |
| 6946874 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Ralph D. Wittig, Jennifer Wong, David B. Squires | 2005-09-20 |
| 6803786 | Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks | Ralph D. Wittig, Jennifer Wong, David B. Squires | 2004-10-12 |
| 6703862 | Efficient loadable registers in programmable logic devices | — | 2004-03-09 |
| 6617876 | Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers | — | 2003-09-09 |
| 6476634 | ALU implementation in single PLD logic cell | — | 2002-11-05 |
| 6477699 | Electronic circuit designs adaptable for applications having different binary data formats | — | 2002-11-05 |