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Data processing engines with cascade connected cores |
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Method and system for function acceleration using custom instructions |
Sundararajarao Mohan, Satish R. Ganesan |
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Method and system to recreate instruction and data traces in an embedded processor |
Jorge Ernesto Carrillo, Usha Prabhu, Navaneethan Sundaramoorthy |
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Method and circuit for decoding an address of an address space |
Paulo L. Dutra, Jorge Ernesto Carrillo |
2008-09-16 |
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Method and system for transferring data between a register in a processor and a point-to-point communication link |
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2008-05-27 |
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Method and system for fast linked processor in a system on a chip (SoC) |
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2008-03-04 |
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Method and apparatus for power optimization during an integrated circuit design process |
Patrick Lysaght, Tim Tuan |
2007-07-10 |
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Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks |
Ralph D. Wittig, Jennifer Wong, David B. Squires |
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Generating fast logic simulation models for a PLD design description |
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Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks |
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2005-09-20 |
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Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks |
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Efficient loadable registers in programmable logic devices |
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2004-03-09 |
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Structures and methods for distributing high-fanout signals in FPGAs using carry multiplexers |
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2003-09-09 |
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ALU implementation in single PLD logic cell |
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2002-11-05 |
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Electronic circuit designs adaptable for applications having different binary data formats |
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2002-11-05 |