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USPTO Patent Rankings Data through Dec 31, 2025
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David Clarke — 16 Patents

AMD: 16 patents #716 of 9,280Top 8%
Dublin, IE: #82 of 2,339 inventorsTop 4%
Overall (All Time): #284,196 of 4,157,543Top 7%
16 Patents All Time
David Clarke has been granted 16 US patents while listed as an inventor at AMD. The first was granted in 2020 and the most recent in August 2025. David Clarke ranks #284,196 of 4,157,543 US inventors in our database (top 6.8%). Patent records list David Clarke in Dublin, IE.

Issued Patents All Time

Showing 1–16 of 16 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
12401364 Multiple partitions in a data processing array Juan J. Noguera Serra, Tim Tuan, Javier Cabezas Rodriguez, Peter McColgan, Zachary Blaise Dickman +3 more 2025-08-26
12164451 Data processing array interface having interface tiles with multiple direct memory access circuits Peter McColgan, Juan J. Noguera Serra, Tim Tuan, Saurabh Mathur, Amarnath Kasibhatla +3 more 2024-12-10
12067406 Multiple overlays for use with a data processing array Baris Ozgul, Peter McColgan, Stephan Munz, Dylan Stuart, Pedro Miguel Parola Duarte +1 more 2024-08-20
11972132 Data processing engine arrangement in a device Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Richard L. Walke +3 more 2024-04-30
11848670 Multiple partitions in a data processing array Juan J. Noguera Serra, Tim Tuan, Javier Cabezas Rodriguez, Peter McColgan, Zachary Blaise Dickman +3 more 2023-12-19
11730325 Dual mode interconnect Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul 2023-08-22
11669464 Multi-addressing mode for DMA and non-sequential read and write patterns Goran H K Bilski, Baris Ozgul, Juan J. Noguera Serra, Jan Langer, Zachary Blaise Dickman +2 more 2023-06-06
11567881 Event-based debug, trace, and profile in device with data processing engine array Goran H K Bilski, Baris Ozgul, Jan Langer, Juan J. Noguera Serra 2023-01-31
11520717 Memory tiles in data processing engine array Peter McColgan, Zachary Blaise Dickman, Jose Marques, Juan J. Noguera Serra, Tim Tuan +2 more 2022-12-06
11443091 Data processing engines with cascade connected cores Peter McColgan, Baris Ozgul, Tim Tuan, Juan J. Noguera Serra, Goran Bilski +4 more 2022-09-13
11372803 Data processing engine tile architecture for an integrated circuit Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Sneha Bhalchandra Date 2022-06-28
11336287 Data processing engine array architecture with memory tiles Javier Cabezas Rodriguez, Juan J. Noguera Serra, Sneha Bhalchandra Date, Tim Tuan, Peter McColgan +2 more 2022-05-17
11323391 Multi-port stream switch for stream interconnect network Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer +1 more 2022-05-03
11113223 Dual mode interconnect Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul 2021-09-07 $55,935,000
10866753 Data processing engine arrangement in a device Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Tim Tuan +3 more 2020-12-15 $77,795,000
10635622 System-on-chip interface architecture Goran H K Bilski, Juan J. Noguera Serra, Tim Tuan, Peter McColgan, Zachary Blaise Dickman +2 more 2020-04-28 $32,103,000