Issued Patents All Time
Showing 1–8 of 8 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12401364 | Multiple partitions in a data processing array | Tim Tuan, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman +3 more | 2025-08-26 |
| 11848670 | Multiple partitions in a data processing array | Tim Tuan, Javier Cabezas Rodriguez, David Clarke, Peter McColgan, Zachary Blaise Dickman +3 more | 2023-12-19 |
| 11669464 | Multi-addressing mode for DMA and non-sequential read and write patterns | Goran H K Bilski, Baris Ozgul, David Clarke, Jan Langer, Zachary Blaise Dickman +2 more | 2023-06-06 |
| 11520717 | Memory tiles in data processing engine array | David Clarke, Peter McColgan, Zachary Blaise Dickman, Jose Marques, Tim Tuan +2 more | 2022-12-06 |
| 11443091 | Data processing engines with cascade connected cores | Peter McColgan, Baris Ozgul, David Clarke, Tim Tuan, Goran Bilski +4 more | 2022-09-13 |
| 11386020 | Programmable device having a data processing engine (DPE) array | Matthew H. Klein, Goran H K Bilski, Ismed D. Hartanto, Sridhar Subramanian, Tim Tuan | 2022-07-12 |
| 11323391 | Multi-port stream switch for stream interconnect network | Peter McColgan, David Clarke, Goran H K Bilski, Baris Ozgul, Jan Langer +1 more | 2022-05-03 |
| 7979818 | Packet processing validation | Robert P. Esser | 2011-07-12 |