Issued Patents All Time
Showing 25 most recent of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12105667 | Device with data processing engine array that enables partial reconfiguration | Juan J. Noguera Serra, Sneha Bhalchandra Date, Baris Ozgul, Goran H K Bilski | 2024-10-01 |
| 11972132 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Baris Ozgul, Richard L. Walke, Ralph D. Wittig +3 more | 2024-04-30 |
| 11853235 | Communicating between data processing engines using shared memory | Juan J. Noguera Serra, Goran H K Bilski, Baris Ozgul | 2023-12-26 |
| 11730325 | Dual mode interconnect | Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, David Clarke | 2023-08-22 |
| 11669464 | Multi-addressing mode for DMA and non-sequential read and write patterns | Goran H K Bilski, Baris Ozgul, David Clarke, Juan J. Noguera Serra, Zachary Blaise Dickman +2 more | 2023-06-06 |
| 11599498 | Device with data processing engine array that enables partial reconfiguration | Juan J. Noguera Serra, Sneha Bhalchandra Date, Baris Ozgul, Goran H K Bilski | 2023-03-07 |
| 11573726 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Baris Ozgul, Richard L. Walke, Ralph D. Wittig +3 more | 2023-02-07 |
| 11567881 | Event-based debug, trace, and profile in device with data processing engine array | Goran H K Bilski, David Clarke, Baris Ozgul, Juan J. Noguera Serra | 2023-01-31 |
| 11520717 | Memory tiles in data processing engine array | David Clarke, Peter McColgan, Zachary Blaise Dickman, Jose Marques, Juan J. Noguera Serra +2 more | 2022-12-06 |
| 11443091 | Data processing engines with cascade connected cores | Peter McColgan, Baris Ozgul, David Clarke, Tim Tuan, Juan J. Noguera Serra +4 more | 2022-09-13 |
| 11379389 | Communicating between data processing engines using shared memory | Juan J. Noguera Serra, Goran H K Bilski, Baris Ozgul | 2022-07-05 |
| 11372803 | Data processing engine tile architecture for an integrated circuit | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, David Clarke, Sneha Bhalchandra Date | 2022-06-28 |
| 11336287 | Data processing engine array architecture with memory tiles | Javier Cabezas Rodriguez, Juan J. Noguera Serra, David Clarke, Sneha Bhalchandra Date, Tim Tuan +2 more | 2022-05-17 |
| 11323391 | Multi-port stream switch for stream interconnect network | Peter McColgan, David Clarke, Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul +1 more | 2022-05-03 |
| 11113223 | Dual mode interconnect | Peter McColgan, Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, David Clarke | 2021-09-07 |
| 11084459 | Driving authorization system | Daniel Deparis, Jakob LUICKHARDT, Markus Rossmann, Gabriele Galwas | 2021-08-10 |
| 11061673 | Data selection network for a data processing engine in an integrated circuit | Baris Ozgul, Juan J. Noguera Serra, Goran H K Bilski, Richard L. Walke | 2021-07-13 |
| 11016822 | Cascade streaming between data processing engines in an array | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Richard L. Walke | 2021-05-25 |
| 10990552 | Streaming interconnect architecture for data processing engine array | Goran H K Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Richard L. Walke +4 more | 2021-04-27 |
| 10866753 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Baris Ozgul, Tim Tuan, Richard L. Walke +3 more | 2020-12-15 |
| 10824584 | Device with data processing engine array that enables partial reconfiguration | Juan J. Noguera Serra, Sneha Bhalchandra Date, Baris Ozgul, Goran H K Bilski | 2020-11-03 |
| 10747531 | Core for a data processing engine in an integrated circuit | Baris Ozgul, Juan J. Noguera Serra, Goran H K Bilski, Tim Tuan | 2020-08-18 |
| 10747690 | Device with data processing engine array | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Richard L. Walke, Ralph D. Wittig +3 more | 2020-08-18 |
| 10635622 | System-on-chip interface architecture | Goran H K Bilski, Juan J. Noguera Serra, David Clarke, Tim Tuan, Peter McColgan +2 more | 2020-04-28 |
| 10579559 | Stall logic for a data processing engine in an integrated circuit | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul | 2020-03-03 |