Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11972132 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Ralph D. Wittig +3 more | 2024-04-30 |
| 11721373 | Shared multi-port memory from single port | John McGrath | 2023-08-08 |
| 11573726 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Ralph D. Wittig +3 more | 2023-02-07 |
| 11348624 | Shared multi-port memory from single port | John McGrath | 2022-05-31 |
| 11108410 | User-programmable LDPC decoder | Christopher H. Dick, Nihat E. Tunali | 2021-08-31 |
| 11082067 | System and method for determining bit types for polar encoding and decoding | Ming Ruan, Gordon I. Old, Zahid Khan | 2021-08-03 |
| 11075650 | Sub-matrix reduction for quasi-cyclic LDPC codes | Andrew Dow | 2021-07-27 |
| 11061673 | Data selection network for a data processing engine in an integrated circuit | Baris Ozgul, Jan Langer, Juan J. Noguera Serra, Goran H K Bilski | 2021-07-13 |
| 11016822 | Cascade streaming between data processing engines in an array | Goran H K Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul | 2021-05-25 |
| 10990552 | Streaming interconnect architecture for data processing engine array | Goran H K Bilski, Peter McColgan, Juan J. Noguera Serra, Baris Ozgul, Jan Langer +4 more | 2021-04-27 |
| 10866753 | Data processing engine arrangement in a device | Juan J. Noguera Serra, Goran H K Bilski, Jan Langer, Baris Ozgul, Tim Tuan +3 more | 2020-12-15 |
| 10833704 | Low-density parity check decoder using encoded no-operation instructions | Andrew Dow, Zahid Khan | 2020-11-10 |
| 10797727 | Low-density parity-check (LDPC) encode using an LDPC decoder | Andrew Dow, Andrew Whyte, Nihat E. Tunali | 2020-10-06 |
| 10747690 | Device with data processing engine array | Goran H K Bilski, Juan J. Noguera Serra, Baris Ozgul, Jan Langer, Ralph D. Wittig +3 more | 2020-08-18 |
| 10727869 | Efficient method for packing low-density parity-check (LDPC) decode operations | Andrew Dow | 2020-07-28 |
| 10673564 | Software defined modem | Christopher H. Dick, William A. Wilkie | 2020-06-02 |
| 10644725 | Interleaved data block processing in low-density parity-check (LDPC) encoder and decoder | Andrew Dow, Andrew Whyte | 2020-05-05 |
| 10484021 | Log-likelihood ratio processing for linear block code decoding | Gordon I. Old | 2019-11-19 |
| 10484012 | Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codes | Nihat E. Tunali, Christopher H. Dick | 2019-11-19 |
| 9778905 | Multiplier circuits configurable for real or complex operation | — | 2017-10-03 |
| 9081634 | Digital signal processing block | James M. Simkins, Wayne E. Wennekamp, John M. Thendean, Adam Elkins | 2015-07-14 |
| 8463835 | Circuit for and method of providing a floating-point adder | — | 2013-06-11 |
| 8365109 | Determining efficient buffering for multi-dimensional datastream applications | Thomas Paul Perry | 2013-01-29 |
| 8250342 | Digital signal processing engine | Igor Kostarnov | 2012-08-21 |