Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks

Structures and methods providing columns of tightly coupled processor and RAM blocks within an array of logic blocks

US Patent 7181718 · Granted Feb 20, 2007

Estimated economic value: $15,043,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Reclamation of memory ECC bits for error tolerant number formats2025
Data processing engine arrangement in a device2024
Control and reconfiguration of data flow graphs on heterogeneous computing platf2023
Data processing engine arrangement in a device2023
Data processing engines with cascade connected cores2022
Control and reconfiguration of data flow graphs on heterogeneous computing platf2022
Dataflow graph programming environment for a heterogenous processing system2021
Streaming interconnect architecture for data processing engine array2021
Data processing engine arrangement in a device2020
Compilation flow for a heterogeneous multi-core architecture2020
Dynamically structured single instruction, multiple data (SIMD) instructions2020
Control and reconfiguration of data flow graphs on heterogeneous computing platf2020