Issued Patents All Time
Showing 1–25 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11743051 | Blockchain machine compute acceleration engine with a block verify and a block validate | Haris Javaid, Ji Yang, Gordon J. Brebner | 2023-08-29 |
| 11657040 | Blockchain machine network acceleration engine | Ji Yang, Haris Javaid, Gordon J. Brebner | 2023-05-23 |
| 11024583 | Integration of a programmable device and a processing system in an integrated circuit package | Austin H. Lesea, Stephen M. Trimberger | 2021-06-01 |
| 10740146 | Migrating virtual machines between compute systems by transmitting programmable logic accelerator state | — | 2020-08-11 |
| 10573598 | Integration of a programmable device and a processing system in an integrated circuit package | Austin H. Lesea, Stephen M. Trimberger | 2020-02-25 |
| 10474599 | Striped direct memory access circuit | — | 2019-11-12 |
| 9880966 | Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit | L. James Hwang, Vinod K. Kathail, Jorge Ernesto Carrillo, Hua Sun | 2018-01-30 |
| 9805152 | Compilation of system designs | Jorge Ernesto Carrillo, Vinod K. Kathail, L. James Hwang, Hua Sun | 2017-10-31 |
| 9652570 | Automatic implementation of a customized system-on-chip | Vinod K. Kathail, L. James Hwang, Jorge Ernesto Carrillo, Hua Sun, Tom Shui +1 more | 2017-05-16 |
| 9557795 | Multiprocessor system with performance control based on input and output data rates | Sabih Sabih | 2017-01-31 |
| 9444497 | Method and apparatus for adaptively tuning an integrated circuit | Tim Tuan | 2016-09-13 |
| 9223921 | Compilation of HLL code with hardware accelerated functions | Jorge Ernesto Carrillo, L. James Hwang, Hua Sun, Vinod K. Kathail | 2015-12-29 |
| 9147024 | Hardware and software cosynthesis performance estimation | Vinod K. Kathail, Hua Sun, L. James Hwang, Yogesh Laxmikant Chobe | 2015-09-29 |
| 8775986 | Software debugging of synthesized hardware | L. James Hwang | 2014-07-08 |
| 8762916 | Automatic generation of a data transfer network | Vinod K. Kathail, L. James Hwang, Hua Sun | 2014-06-24 |
| 8327200 | Integrated circuit providing improved feed back of a signal | — | 2012-12-04 |
| 7721090 | Event-driven simulation of IP using third party event-driven simulators | Kumar Deepak, Satish R. Ganesan, Jimmy Zhenming Wang, Ralph D. Wittig, Hem C. Neema | 2010-05-18 |
| 7676661 | Method and system for function acceleration using custom instructions | Satish R. Ganesan, Goran Bilski | 2010-03-09 |
| 7310594 | Method and system for designing a multiprocessor | Satish R. Ganesan, Usha Prabhu, Ralph D. Wittig, David W. Bennett | 2007-12-18 |
| 7248073 | Configurable logic element with expander structures | Bernard J. New, Ralph D. Wittig | 2007-07-24 |
| 7243330 | Method and apparatus for providing self-implementing hardware-software libraries | Satish R. Ganesan, Amit Kasat, Sathyanarayanan Thammanur, Usha Prabhu, Ralph D. Wittig | 2007-07-10 |
| 7145360 | Configurable logic element with expander structures | Bernard J. New, Ralph D. Wittig | 2006-12-05 |
| 7111273 | Softpal implementation and mapping technology for FPGAs with dedicated resources | Satish R. Ganesan, Ralph D. Wittig | 2006-09-19 |
| 6847229 | Configurable logic element with expander structures | Bernard J. New, Ralph D. Wittig | 2005-01-25 |
| 6630841 | Configurable logic element with expander structures | Bernard J. New, Ralph D. Wittig | 2003-10-07 |