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Circuit arrangement for profiling a programmable processor connected via a uni-directional bus |
Sivakumar Velusamy, Navaneethan Sundaramoorthy, Raj Nagarajan |
2010-11-23 |
| 7721090 |
Event-driven simulation of IP using third party event-driven simulators |
Kumar Deepak, Jimmy Zhenming Wang, Sundararajarao Mohan, Ralph D. Wittig, Hem C. Neema |
2010-05-18 |
| 7676661 |
Method and system for function acceleration using custom instructions |
Sundararajarao Mohan, Goran Bilski |
2010-03-09 |
| 7606694 |
Framework for cycle accurate simulation |
Jorge Ernesto Carrillo, Amit Kasat, Sivakumar Velusamy |
2009-10-20 |
| 7426709 |
Auto-generation and placement of arbitration logic in a multi-master multi-slave embedded system |
— |
2008-09-16 |
| 7340585 |
Method and system for fast linked processor in a system on a chip (SoC) |
Goran Bilski, Usha Prabhu, Ralph D. Wittig |
2008-03-04 |
| 7310594 |
Method and system for designing a multiprocessor |
Usha Prabhu, Sundararajarao Mohan, Ralph D. Wittig, David W. Bennett |
2007-12-18 |
| 7243330 |
Method and apparatus for providing self-implementing hardware-software libraries |
Amit Kasat, Sathyanarayanan Thammanur, Sundararajarao Mohan, Usha Prabhu, Ralph D. Wittig |
2007-07-10 |
| 7131091 |
Generating fast logic simulation models for a PLD design description |
Goran Bilski, Usha Prabhu, Paulo L. Dutra |
2006-10-31 |
| 7111273 |
Softpal implementation and mapping technology for FPGAs with dedicated resources |
Sundararajarao Mohan, Ralph D. Wittig |
2006-09-19 |
| 6833730 |
PLD configurable logic block enabling the rapid calculation of sum-of-products functions |
Amit Kasat |
2004-12-21 |