Issued Patents All Time
Showing 25 most recent of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12050944 | Network attached MPI processing architecture in smartnics | Guanwen Zhong, Chengchen Hu | 2024-07-30 |
| 11831743 | Streaming architecture for packet parsing | Jaime Herrera, Ian McBryan, Rowan Lyons | 2023-11-28 |
| 11743051 | Blockchain machine compute acceleration engine with a block verify and a block validate | Haris Javaid, Ji Yang, Sundararajarao Mohan | 2023-08-29 |
| 11743134 | Programmable traffic management engine | Guanwen Zhong, Chengchen Hu | 2023-08-29 |
| 11657040 | Blockchain machine network acceleration engine | Ji Yang, Haris Javaid, Sundararajarao Mohan | 2023-05-23 |
| 11641323 | Programmable congestion control engine | Nguyen Duy Anh Tuan, Ji Yang, Chengchen Hu, Yan Zhang, Guanwen Zhong | 2023-05-02 |
| 11431815 | Mining proxy acceleration | Guanwen Zhong, Haris Javaid, Chengchen Hu, Ji Yang | 2022-08-30 |
| 11425036 | Pipelined match-action circuitry | Jaime Herrera, Ian McBryan, Rowan Lyons | 2022-08-23 |
| 11290361 | Programmable network measurement engine | Chengchen Hu, Ji Yang, Yan Zhang, Siyi Qiao | 2022-03-29 |
| 10834241 | Streaming editor circuit for implementing a packet deparsing process | Ian McBryan, Jaime Herrera, Rowan Lyons | 2020-11-10 |
| 9674081 | Efficient mapping of table pipelines for software-defined networking (SDN) data plane | Weirong Jiang | 2017-06-06 |
| 9350385 | Modular and scalable cyclic redundancy check computation circuit | Weirong Jiang, Mark Carson | 2016-05-24 |
| 9270517 | Tuple construction from data packets | Michael E. Attig | 2016-02-23 |
| 9110524 | High throughput finite state machine | Weirong Jiang, Yi-Hua Edward Yang | 2015-08-18 |
| 8874837 | Embedded memory and dedicated processor structure within an integrated circuit | Christopher E. Neely | 2014-10-28 |
| 8780914 | Parallel processing of network packets | — | 2014-07-15 |
| 8775685 | Parallel processing of network packets | — | 2014-07-08 |
| 8560996 | Method and system for preparing modularized circuit designs for dynamic partial reconfiguration of programmable logic | Christopher E. Neely | 2013-10-15 |
| 8443102 | Pipeline of a packet processor programmed to extract packet fields | Michael E. Attig | 2013-05-14 |
| 8385340 | Pipeline of a packet processor programmed to concurrently perform operations | Michael E. Attig | 2013-02-26 |
| 8358653 | Generating a pipeline of a packet processor from a parsing tree | Michael E. Attig | 2013-01-22 |
| 8311057 | Managing formatting of packets of a communication protocol | Michael E. Attig | 2012-11-13 |
| 8266583 | Flexible packet data storage for diverse packet processing applications | — | 2012-09-11 |
| 8160092 | Transforming a declarative description of a packet processor | Michael E. Attig | 2012-04-17 |
| 8144702 | Generation of a pipeline for processing a type of network packets | Michael E. Attig | 2012-03-27 |