Issued Patents All Time
Showing 26–50 of 51 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6603332 | Configurable logic block for PLD with logic gate for combining output with another configurable logic block | Alireza S. Kaviani, Ralph D. Wittig, Steven P. Young, Bernard J. New | 2003-08-05 |
| 6583645 | Field programmable optical arrays | David W. Bennett, Ralph D. Wittig | 2003-06-24 |
| 6505337 | Method for implementing large multiplexers with FPGA lookup tables | Ralph D. Wittig | 2003-01-07 |
| 6501296 | Logic/memory circuit having a plurality of operating modes | Ralph D. Wittig, Richard A. Carberry | 2002-12-31 |
| 6457164 | Hetergeneous method for determining module placement in FPGAs | L. James Hwang, Eric F. Dellinger, Sujoy Mitra, Cameron Patterson, Ralph D. Wittig | 2002-09-24 |
| 6421817 | System and method of computation in a programmable logic device using virtual instructions | Stephen M. Trimberger | 2002-07-16 |
| 6400180 | Configurable lookup table for programmable logic devices | Ralph D. Wittig, Bernard J. New | 2002-06-04 |
| 6396302 | Configurable logic element with expander structures | Bernard J. New, Ralph D. Wittig | 2002-05-28 |
| 6388466 | FPGA logic element with variable-length shift register capability | Ralph D. Wittig, Bernard J. New | 2002-05-14 |
| 6353920 | Method for implementing wide gates and tristate buffers using FPGA carry logic | Ralph D. Wittig, Hamish T. Fallside | 2002-03-05 |
| 6336208 | Delay optimized mapping for programmable gate arrays with multiple sized lookup tables | Kamal Chaudhary | 2002-01-01 |
| 6292925 | Context-sensitive self implementing modules | Eric F. Dellinger, L. James Hwang, Sujoy Mitra, Ralph D. Wittig | 2001-09-18 |
| 6288569 | Memory array with hard and soft decoders | Ralph D. Wittig, Richard A. Carberry | 2001-09-11 |
| 6259205 | High-pressure discharge lamp with a discharge vessel having conical of concentric ends | Christoffel Wijenberg, Bernardus Lambertus Martinus Van Bakel, Ralph D. Wittig | 2001-07-10 |
| 6260182 | Method for specifying routing in a logic module by direct module communication | Eric F. Dellinger, L. James Hwang, Sujoy Mitra, Ralph D. Wittig | 2001-07-10 |
| 6255849 | On-chip self-modification for PLDs | — | 2001-07-03 |
| 6243851 | Heterogeneous method for determining module placement in FPGAs | L. James Hwang, Eric F. Dellinger, Sujoy Mitra, Cameron Patterson, Ralph D. Wittig | 2001-06-05 |
| 6237129 | Method for constraining circuit element positions in structured layouts | Cameron Patterson, Eric F. Dellinger, L. James Hwang, Sujoy Mitra, Ralph D. Wittig | 2001-05-22 |
| 6216258 | FPGA modules parameterized by expressions | Eric F. Dellinger, L. James Hwang, Sujoy Mitra, Ralph D. Wittig | 2001-04-10 |
| 6208163 | FPGA configurable logic block with multi-purpose logic/memory circuit | Ralph D. Wittig, Richard A. Carberry | 2001-03-27 |
| 6191610 | Method for implementing large multiplexers with FPGA lookup tables | Ralph D. Wittig | 2001-02-20 |
| 6184712 | FPGA configurable logic block with multi-purpose logic/memory circuit | Ralph D. Wittig, Richard A. Carberry | 2001-02-06 |
| 6150838 | FPGA configurable logic block with multi-purpose logic/memory circuit | Ralph D. Wittig, Richard A. Carberry | 2000-11-21 |
| 6118300 | Method for implementing large multiplexers with FPGA lookup tables | Ralph D. Wittig | 2000-09-12 |
| 6091263 | Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM | Bernard J. New, Robert Anders Johnson, Ralph D. Wittig | 2000-07-18 |