Issued Patents All Time
Showing 25 most recent of 29 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7317773 | Double data rate flip-flop | Steven P. Young, Suresh M. Menon, Ketan Sodha, Joseph H. Hassoun | 2008-01-08 |
| 6777980 | Double data rate flip-flop | Steven P. Young, Suresh M. Menon, Ketan Sodha, Joseph H. Hassoun | 2004-08-17 |
| 6621296 | FPGA lookup table with high speed read decorder | Steven P. Young, Trevor J. Bauer | 2003-09-16 |
| 6529040 | FPGA lookup table with speed read decoder | Steven P. Young, Trevor J. Bauer | 2003-03-04 |
| 6525565 | Double data rate flip-flop | Steven P. Young, Suresh M. Menon, Ketan Sodha, Joseph H. Hassoun | 2003-02-25 |
| 6501296 | Logic/memory circuit having a plurality of operating modes | Ralph D. Wittig, Sundararajarao Mohan | 2002-12-31 |
| 6480954 | Method of time multiplexing a programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 2002-11-12 |
| 6445209 | FPGA lookup table with NOR gate write decoder and high speed read decoder | Steven P. Young, Trevor J. Bauer | 2002-09-03 |
| 6373279 | FPGA lookup table with dual ended writes for ram and shift register modes | Trevor J. Bauer, Steven P. Young | 2002-04-16 |
| 6292019 | Programmable logic device having configurable logic blocks with user-accessible input multiplexers | Bernard J. New | 2001-09-18 |
| 6288569 | Memory array with hard and soft decoders | Ralph D. Wittig, Sundararajarao Mohan | 2001-09-11 |
| 6263430 | Method of time multiplexing a programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 2001-07-17 |
| 6208163 | FPGA configurable logic block with multi-purpose logic/memory circuit | Ralph D. Wittig, Sundararajarao Mohan | 2001-03-27 |
| 6184712 | FPGA configurable logic block with multi-purpose logic/memory circuit | Ralph D. Wittig, Sundararajarao Mohan | 2001-02-06 |
| 6150838 | FPGA configurable logic block with multi-purpose logic/memory circuit | Ralph D. Wittig, Sundararajarao Mohan | 2000-11-21 |
| 6078528 | Delay control circuit using dynamic latches | Robert Anders Johnson, Scott K. Roberts | 2000-06-20 |
| 5978260 | Method of time multiplexing a programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1999-11-02 |
| 5959881 | Programmable logic device including configuration data or user data memory slices | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1999-09-28 |
| 5933369 | RAM with synchronous write port using dynamic latches | Robert Anders Johnson, Scott K. Roberts | 1999-08-03 |
| 5784313 | Programmable logic device including configuration data or user data memory slices | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1998-07-21 |
| 5778439 | Programmable logic device with hierarchical confiquration and state storage | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1998-07-07 |
| 5646545 | Time multiplexed programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1997-07-08 |
| 5629637 | Method of time multiplexing a programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1997-05-13 |
| 5600263 | Configuration modes for a time multiplexed programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1997-02-04 |
| 5583450 | Sequencer for a time multiplexed programmable logic device | Stephen M. Trimberger, Robert Anders Johnson, Jennifer Wong | 1996-12-10 |