| 11133145 |
Draw-out current limiting fuse |
— |
2021-09-28 |
|
| 7759973 |
Integrated circuit having embedded differential clock tree |
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele |
2010-07-20 |
$2,876,000 |
| 7617472 |
Regional signal-distribution network for an integrated circuit |
Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Atul V. Ghia, Steven P. Young +1 more |
2009-11-10 |
$24,816,000 |
| 7551646 |
Data alignment and deskewing module |
Qi Zhang, Jason R. Bergendahl, Atul V. Ghia |
2009-06-23 |
$5,693,000 |
| 7518401 |
Differential clock tree in an integrated circuit |
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele |
2009-04-14 |
$6,987,000 |
| 7414430 |
Programmable logic device having an embedded differential clock tree |
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele |
2008-08-19 |
$47,581,000 |
| 7372299 |
Differential clock tree in an integrated circuit |
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele |
2008-05-13 |
$7,850,000 |
| 7353487 |
Regional signal-distribution network for an integrated circuit |
Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Atul V. Ghia, Steven P. Young +1 more |
2008-04-01 |
$8,251,000 |
| 7317773 |
Double data rate flip-flop |
Steven P. Young, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun |
2008-01-08 |
$13,828,000 |
| 7187709 |
High speed configurable transceiver architecture |
Atul V. Ghia, Warren E. Cory, Paul T. Sasaki, Philip M. Freidin, Santiago G. Asuncion +4 more |
2007-03-06 |
$5,029,000 |
| 7129765 |
Differential clock tree in an integrated circuit |
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele |
2006-10-31 |
$11,476,000 |
| 7126406 |
Programmable logic device having an embedded differential clock tree |
Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele |
2006-10-24 |
$12,015,000 |
| 7111220 |
Network physical layer with embedded multi-standard CRC generator |
Paul T. Sasaki, Atul V. Ghia, Warren E. Cory, Hare K. Verma, Philip M. Freidin |
2006-09-19 |
$3,343,000 |
| 7091890 |
Multi-purpose source synchronous interface circuitry |
Paul T. Sasaki, Jason R. Bergendahl, Atul V. Ghia, Hassan K. Bazargan, Ketan Sodha +2 more |
2006-08-15 |
$5,442,000 |
| 6960933 |
Variable data width operation in multi-gigabit transceivers on a programmable logic device |
Warren E. Cory, Hare K. Verma, Atul V. Ghia, Paul T. Sasaki |
2005-11-01 |
$8,703,000 |
| 6810458 |
Method and circuit for hot swap protection |
Hassan K. Bazargan, Jian Tan, Atul V. Ghia |
2004-10-26 |
$9,560,000 |
| 6777980 |
Double data rate flip-flop |
Steven P. Young, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun |
2004-08-17 |
$37,875,000 |
| 6617877 |
Variable data width operation in multi-gigabit transceivers on a programmable logic device |
Warren E. Cory, Hare K. Verma, Atul V. Ghia, Paul T. Sasaki |
2003-09-09 |
$21,199,000 |
| 6525565 |
Double data rate flip-flop |
Steven P. Young, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun |
2003-02-25 |
$13,505,000 |
| 6501677 |
Configuration memory architecture for FPGA |
Prasad Rau, Atul V. Ghia |
2002-12-31 |
$13,489,000 |
| 6489837 |
Digitally controlled impedance for I/O of an integrated circuit device |
David P. Schultz, Eunice Y. D. Hao, Jason R. Bergendahl, Jian Tan |
2002-12-03 |
$39,171,000 |
| 6445245 |
Digitally controlled impedance for I/O of an integrated circuit device |
David P. Schultz, Eunice Y. D. Hao, Jason R. Bergendahl, Jian Tan |
2002-09-03 |
$19,444,000 |
| 6366128 |
Circuit for producing low-voltage differential signals |
Atul V. Ghia, David P. Schultz |
2002-04-02 |
$73,316,000 |
| 6222757 |
Configuration memory architecture for FPGA |
Prasad Rau, Atul V. Ghia |
2001-04-24 |
$138,864,000 |
| 6218858 |
Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits |
Yogendra Bobra, Atul V. Ghia, Arch Zaliznyak |
2001-04-17 |
$57,440,000 |
