Issued Patents All Time
Showing 25 most recent of 35 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11133145 | Draw-out current limiting fuse | — | 2021-09-28 |
| 7759973 | Integrated circuit having embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele | 2010-07-20 |
| 7617472 | Regional signal-distribution network for an integrated circuit | Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Atul V. Ghia, Steven P. Young +1 more | 2009-11-10 |
| 7551646 | Data alignment and deskewing module | Qi Zhang, Jason R. Bergendahl, Atul V. Ghia | 2009-06-23 |
| 7518401 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele | 2009-04-14 |
| 7414430 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele | 2008-08-19 |
| 7372299 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele | 2008-05-13 |
| 7353487 | Regional signal-distribution network for an integrated circuit | Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Atul V. Ghia, Steven P. Young +1 more | 2008-04-01 |
| 7317773 | Double data rate flip-flop | Steven P. Young, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2008-01-08 |
| 7187709 | High speed configurable transceiver architecture | Atul V. Ghia, Warren E. Cory, Paul T. Sasaki, Philip M. Freidin, Santiago G. Asuncion +4 more | 2007-03-06 |
| 7129765 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele | 2006-10-31 |
| 7126406 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Adebabay M. Bekele | 2006-10-24 |
| 7111220 | Network physical layer with embedded multi-standard CRC generator | Paul T. Sasaki, Atul V. Ghia, Warren E. Cory, Hare K. Verma, Philip M. Freidin | 2006-09-19 |
| 7091890 | Multi-purpose source synchronous interface circuitry | Paul T. Sasaki, Jason R. Bergendahl, Atul V. Ghia, Hassan K. Bazargan, Ketan Sodha +2 more | 2006-08-15 |
| 6960933 | Variable data width operation in multi-gigabit transceivers on a programmable logic device | Warren E. Cory, Hare K. Verma, Atul V. Ghia, Paul T. Sasaki | 2005-11-01 |
| 6810458 | Method and circuit for hot swap protection | Hassan K. Bazargan, Jian Tan, Atul V. Ghia | 2004-10-26 |
| 6777980 | Double data rate flip-flop | Steven P. Young, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2004-08-17 |
| 6617877 | Variable data width operation in multi-gigabit transceivers on a programmable logic device | Warren E. Cory, Hare K. Verma, Atul V. Ghia, Paul T. Sasaki | 2003-09-09 |
| 6525565 | Double data rate flip-flop | Steven P. Young, Ketan Sodha, Richard A. Carberry, Joseph H. Hassoun | 2003-02-25 |
| 6501677 | Configuration memory architecture for FPGA | Prasad Rau, Atul V. Ghia | 2002-12-31 |
| 6489837 | Digitally controlled impedance for I/O of an integrated circuit device | David P. Schultz, Eunice Y. D. Hao, Jason R. Bergendahl, Jian Tan | 2002-12-03 |
| 6445245 | Digitally controlled impedance for I/O of an integrated circuit device | David P. Schultz, Eunice Y. D. Hao, Jason R. Bergendahl, Jian Tan | 2002-09-03 |
| 6366128 | Circuit for producing low-voltage differential signals | Atul V. Ghia, David P. Schultz | 2002-04-02 |
| 6222757 | Configuration memory architecture for FPGA | Prasad Rau, Atul V. Ghia | 2001-04-24 |
| 6218858 | Programmable input/output circuit for FPGA for use in TTL, GTL, GTLP, LVPECL and LVDS circuits | Yogendra Bobra, Atul V. Ghia, Arch Zaliznyak | 2001-04-17 |