Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12425107 | Methods and apparatuses for maximizing output modulation amplitude for optical wavelength division multiplexed micro-ring modulators | Mayank Raj, Chuan Xie, Sandeep Kumar, Zhaowen Wang, Sukruth Pattanagiri Giriyappa +2 more | 2025-09-23 |
| 11689207 | Wide frequency range voltage controlled oscillators | Parag Upadhyaya | 2023-06-27 |
| 11637528 | Wide frequency range voltage controlled oscillators | Parag Upadhyaya | 2023-04-25 |
| 10868663 | Flexible wide-range and high bandwidth auxiliary clock and data recovery (CDR) circuit for transceivers | Didem Z. Turker Melek, Mayank Raj, Parag Upadhyaya, Yohan Frans | 2020-12-15 |
| 10715153 | Multi-port inductors and transformers for accurately predicting voltage-controlled oscillator (VCO) frequency | Parag Upadhyaya, Didem Z. Turker Melek, Jing Jing | 2020-07-14 |
| 10630301 | Temperature-dependent phase-locked loop (PLL) reset for clock synthesizers | Parag Upadhyaya, Didem Z. Turker Melek | 2020-04-21 |
| 10623008 | Reconfigurable fractional-N frequency generation for a phase-locked loop | Parag Upadhyaya, Didem Z. Turker Melek, Zhaoyin D. Wu | 2020-04-14 |
| 9742380 | Phase-locked loop having sampling phase detector | Mayank Raj, Parag Upadhyaya | 2017-08-22 |
| 9608644 | Phase-locked loop having sub-sampling phase detector | Mayank Raj, Parag Upadhyaya | 2017-03-28 |
| 9325277 | Voltage controlled oscillator including MuGFETS | Parag Upadhyaya | 2016-04-26 |
| 8614599 | Method and apparatus for powering down a dual supply current source | Aman Sewani, Xuewen Jiang | 2013-12-24 |
| 8218712 | Method and apparatus for dividing clock frequencies | Xuewen Jiang | 2012-07-10 |
| 7759973 | Integrated circuit having embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Suresh M. Menon | 2010-07-20 |
| 7518401 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Suresh M. Menon | 2009-04-14 |
| 7414430 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Suresh M. Menon | 2008-08-19 |
| 7372299 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Suresh M. Menon | 2008-05-13 |
| 7187709 | High speed configurable transceiver architecture | Suresh M. Menon, Atul V. Ghia, Warren E. Cory, Paul T. Sasaki, Philip M. Freidin +4 more | 2007-03-06 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers | Atul V. Ghia | 2006-11-28 |
| 7129765 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Suresh M. Menon | 2006-10-31 |
| 7126406 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Atul V. Ghia, Suresh M. Menon | 2006-10-24 |
| 7061283 | Differential clock driver circuit | Atul V. Ghia | 2006-06-13 |
| 6911842 | Low jitter clock for a physical media access sublayer on a field programmable gate array | Atul V. Ghia, Vasisht Mantra Vadi, Philip D. Costello, Hare K. Verma | 2005-06-28 |