Issued Patents All Time
Showing 25 most recent of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8410579 | Power distribution network | Christopher P. Wyland, Ketan Sodha, Paul T. Sasaki, Jian Tan, Paul Ying-Fung Wu +1 more | 2013-04-02 |
| 8030967 | Method and apparatus involving a receiver with a selectable performance characteristic | Jian Tan, Matthew H. Klein | 2011-10-04 |
| 7759973 | Integrated circuit having embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Adebabay M. Bekele, Suresh M. Menon | 2010-07-20 |
| 7617472 | Regional signal-distribution network for an integrated circuit | Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Suresh M. Menon, Steven P. Young +1 more | 2009-11-10 |
| 7551646 | Data alignment and deskewing module | Qi Zhang, Jason R. Bergendahl, Suresh M. Menon | 2009-06-23 |
| 7518401 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Adebabay M. Bekele, Suresh M. Menon | 2009-04-14 |
| 7480361 | Phase lock detector | Qi Zhang | 2009-01-20 |
| 7414430 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Adebabay M. Bekele, Suresh M. Menon | 2008-08-19 |
| 7372299 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Adebabay M. Bekele, Suresh M. Menon | 2008-05-13 |
| 7353487 | Regional signal-distribution network for an integrated circuit | Jason R. Bergendahl, Ping-Chen Liu, Paul T. Sasaki, Suresh M. Menon, Steven P. Young +1 more | 2008-04-01 |
| 7187709 | High speed configurable transceiver architecture | Suresh M. Menon, Warren E. Cory, Paul T. Sasaki, Philip M. Freidin, Santiago G. Asuncion +4 more | 2007-03-06 |
| 7142033 | Differential clocking scheme in an integrated circuit having digital multiplexers | Adebabay M. Bekele | 2006-11-28 |
| 7129765 | Differential clock tree in an integrated circuit | Vasisht Mantra Vadi, Steven P. Young, Adebabay M. Bekele, Suresh M. Menon | 2006-10-31 |
| 7126406 | Programmable logic device having an embedded differential clock tree | Vasisht Mantra Vadi, Steven P. Young, Adebabay M. Bekele, Suresh M. Menon | 2006-10-24 |
| 7111220 | Network physical layer with embedded multi-standard CRC generator | Paul T. Sasaki, Suresh M. Menon, Warren E. Cory, Hare K. Verma, Philip M. Freidin | 2006-09-19 |
| 7099426 | Flexible channel bonding and clock correction operations on a multi-block data path | Warren E. Cory | 2006-08-29 |
| 7091890 | Multi-purpose source synchronous interface circuitry | Paul T. Sasaki, Jason R. Bergendahl, Hassan K. Bazargan, Ketan Sodha, Jian Tan +2 more | 2006-08-15 |
| 7061283 | Differential clock driver circuit | Adebabay M. Bekele | 2006-06-13 |
| 6985096 | Bimodal serial to parallel converter with bitslip controller | Paul T. Sasaki, Jason R. Bergendahl, Jian Tan | 2006-01-10 |
| 6963219 | Programmable differential internal termination for a low voltage differential signal input or output buffer | Ketan Sodha | 2005-11-08 |
| 6960933 | Variable data width operation in multi-gigabit transceivers on a programmable logic device | Warren E. Cory, Hare K. Verma, Paul T. Sasaki, Suresh M. Menon | 2005-11-01 |
| 6911842 | Low jitter clock for a physical media access sublayer on a field programmable gate array | Vasisht Mantra Vadi, Adebabay M. Bekele, Philip D. Costello, Hare K. Verma | 2005-06-28 |
| 6836142 | Asymmetric bidirectional bus implemented using an I/O device with a digitally controlled impedance | Austin H. Lesea | 2004-12-28 |
| 6836168 | Line driver with programmable slew rates | Austin H. Lesea | 2004-12-28 |
| 6810458 | Method and circuit for hot swap protection | Hassan K. Bazargan, Jian Tan, Suresh M. Menon | 2004-10-26 |