Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12255880 | Cryptographic device, system and method thereof | — | 2025-03-18 |
| 12081531 | Secure communications using loop-based authentication flow | Richard J. Nathan, Harry Leslie Tredennick | 2024-09-03 |
| 12069038 | Encryption and decryption techniques using shuffle function | Richard J. Nathan, Harry Leslie Tredennick | 2024-08-20 |
| 12032676 | Secure hardware signature and related methods and applications | Richard J. Nathan, Harry Leslie Tredennick | 2024-07-09 |
| 11595368 | Secure communications using loop-based authentication flow | Richard J. Nathan, Harry Leslie Tredennick | 2023-02-28 |
| 11544371 | Secure hardware signature and related methods and applications | Richard J. Nathan, Harry Leslie Tredennick | 2023-01-03 |
| 11516201 | Encryption and decryption techniques using shuffle function | Richard J. Nathan, Harry Leslie Tredennick | 2022-11-29 |
| 10931658 | Encryption and decryption techniques using shuffle function | Richard J. Nathan, Harry Leslie Tredennick | 2021-02-23 |
| 10891366 | Secure hardware signature and related methods and applications | Richard J. Nathan, Harry Leslie Tredennick | 2021-01-12 |
| 10742622 | Secure communications using loop-based authentication flow | Richard J. Nathan, Harry Leslie Tredennick | 2020-08-11 |
| 10419416 | Encryption and decryption techniques using shuffle function | Richard J. Nathan, Harry Leslie Tredennick | 2019-09-17 |
| 10263779 | Secure communications using loop-based authentication flow | Richard J. Nathan, Harry Leslie Tredennick | 2019-04-16 |
| 10038259 | Low insertion loss package pin structure and method | Sarajuddin Niazi, Raymond E. Anderson, Suresh Ramalingam | 2018-07-31 |
| 10021085 | Encryption and decryption techniques using shuffle function | Richard J. Nathan, Harry Leslie Tredennick | 2018-07-10 |
| 9635011 | Encryption and decryption techniques using shuffle function | Richard J. Nathan, Harry Leslie Tredennick | 2017-04-25 |
| 9377802 | Dynamic configuration of equivalent series resistance | Christopher P. Wyland, Romi Mayder | 2016-06-28 |
| 9337138 | Capacitors within an interposer coupled to supply and ground planes of a substrate | Khaldoon S. Abugharbieh, Gregory Meredith, Christopher P. Wyland, Henley Liu, Sanjiv Stokes +1 more | 2016-05-10 |
| 9144150 | Conductor structure with integrated via element | — | 2015-09-22 |
| 9006030 | Warpage management for fan-out mold packaged integrated circuit | Woon-Seong Kwon, Suresh Ramalingam, Manoj Nachnani | 2015-04-14 |
| 8743559 | Interconnect pattern for semiconductor packaging | Richard L. Wheeler | 2014-06-03 |
| 8519542 | Air through-silicon via structure | Namhoon Kim, Dong Wook Kim | 2013-08-27 |
| 8410579 | Power distribution network | Atul V. Ghia, Christopher P. Wyland, Ketan Sodha, Paul T. Sasaki, Jian Tan +1 more | 2013-04-02 |
| 8395903 | Interconnect pattern for semiconductor packaging | Richard L. Wheeler | 2013-03-12 |
| 8198724 | Integrated circuit device having a multi-layer substrate and a method of enabling signals to be routed in a multi-layer substrate | Dennis C.P. Leung | 2012-06-12 |
| 8178962 | Semiconductor device package and methods of manufacturing the same | Soon-Shin Chee | 2012-05-15 |