Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12068257 | Integrated circuit (IC) structure protection scheme | Myongseob Kim, Yun Wu, Cheang-Whang Chang | 2024-08-20 |
| 11901338 | Interwafer connection structure for coupling wafers in a wafer stack | Myongseob Kim, Cheang-Whang Chang | 2024-02-13 |
| 11355412 | Stacked silicon package assembly having thermal management | Jaspreet S. Gandhi, Gamal Refai-Ahmed, Myongseob Kim, Tien-Yu Lee, Suresh Ramalingam +1 more | 2022-06-07 |
| 11205639 | Integrated circuit device with stacked dies having mirrored circuitry | Myongseob Kim, Cheang-Whang Chang | 2021-12-21 |
| 11114344 | IC die with dummy structures | Hui-Wen Lin, Nui Chong, Myongseob Kim, Ping-Chin Yeh, Cheang-Whang Chang | 2021-09-07 |
| 11054461 | Test circuits for testing a die stack | Nui Chong, Amitava Majumdar, Cheang-Whang Chang, Myongseob Kim, Albert Shih-Huai Lin | 2021-07-06 |
| 10971474 | Package integration for high bandwidth memory | Jaspreet S. Gandhi | 2021-04-06 |
| 10770430 | Package integration for memory devices | Myongseob Kim, Cheang-Whang Chang, Jaspreet S. Gandhi | 2020-09-08 |
| 10720377 | Electronic device apparatus with multiple thermally conductive paths for heat dissipation | Gamal Refai-Ahmed, Ho Hyung Lee, Hui-Wen Lin, Suresh Ramalingam | 2020-07-21 |
| 10692837 | Chip package assembly with modular core dice | Myongseob Kim, Cheang-Whang Chang, Nui Chong | 2020-06-23 |
| 10629512 | Integrated circuit die with in-chip heat sink | Hong-Tsz Pan, Jonathan Chang, Nui Chong, Gamal Refai-Ahmed, Suresh Ramalingam | 2020-04-21 |
| 10593638 | Methods of interconnect for high density 2.5D and 3D integration | Jaspreet S. Gandhi, Suresh Ramalingam | 2020-03-17 |
| 10529645 | Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management | Jaspreet S. Gandhi, Tien-Yu Lee, Gamal Refai-Ahmed, Myongseob Kim, Ferdinand F. Fernandez +2 more | 2020-01-07 |
| 10527670 | Testing system for lid-less integrated circuit packages | Gamal Refai-Ahmed, Ivor G. Barber, Suresh Ramalingam, Jaspreet S. Gandhi, Tien-Yu Lee +2 more | 2020-01-07 |
| 10431565 | Wafer edge partial die engineered for stacked die yield | Myongseob Kim, Cheang-Whang Chang | 2019-10-01 |
| 10319606 | Chip package assembly with enhanced interconnects and method for fabricating the same | Jaspreet S. Gandhi, Tien-Yu Lee, Ivor G. Barber, Suresh Ramalingam | 2019-06-11 |
| 10262911 | Circuit for and method of testing bond connections between a first die and a second die | Yuqing Gong, Myongseob Kim, Suresh Parameswaran, Cheang-Whang Chang, Boon Yong Ang | 2019-04-16 |
| 9412674 | Shielded wire arrangement for die testing | Myongseob Kim, Cheang-Whang Chang, Sanjiv Stokes | 2016-08-09 |
| 9337138 | Capacitors within an interposer coupled to supply and ground planes of a substrate | Khaldoon S. Abugharbieh, Gregory Meredith, Christopher P. Wyland, Paul Ying-Fung Wu, Sanjiv Stokes +1 more | 2016-05-10 |
| 8810269 | Method of testing a semiconductor structure | Yuqing Gong, Myongseob Kim, Suresh Parameswaran, Cheang-Whang Chang, Boon Yong Ang | 2014-08-19 |
| 8802454 | Methods of manufacturing a semiconductor structure | Arifur Rahman, Cheang-Whang Chang, Myongseob Kim, Dong Wook Kim | 2014-08-12 |
| 8354671 | Integrated circuit with adaptive VGG setting | Hsung Jai Im, Jae-Gyung Ahn, Tony Le, Patrick J. Crotty | 2013-01-15 |