Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12068257 | Integrated circuit (IC) structure protection scheme | Myongseob Kim, Henley Liu, Yun Wu | 2024-08-20 |
| 12045469 | Single event upset tolerant memory device | Kumar Rahul, John Wuu, Santosh Yachareni, Nui Chong | 2024-07-23 |
| 11901338 | Interwafer connection structure for coupling wafers in a wafer stack | Myongseob Kim, Henley Liu | 2024-02-13 |
| 11585854 | Runtime measurement of process variations and supply voltage characteristics | Da-Qing Cheng, Nui Chong, Amitava Majumdar, Ping-Chin Yeh | 2023-02-21 |
| 11488936 | Stacked silicon package assembly having vertical thermal management | Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet S. Gandhi | 2022-11-01 |
| 11355412 | Stacked silicon package assembly having thermal management | Jaspreet S. Gandhi, Gamal Refai-Ahmed, Henley Liu, Myongseob Kim, Tien-Yu Lee +1 more | 2022-06-07 |
| 11205639 | Integrated circuit device with stacked dies having mirrored circuitry | Myongseob Kim, Henley Liu | 2021-12-21 |
| 11145566 | Stacked silicon package assembly having thermal management | Gamal Refai-Ahmed, Suresh Ramalingam, Jaspreet S. Gandhi | 2021-10-12 |
| 11114344 | IC die with dummy structures | Hui-Wen Lin, Nui Chong, Myongseob Kim, Henley Liu, Ping-Chin Yeh | 2021-09-07 |
| 11054461 | Test circuits for testing a die stack | Nui Chong, Amitava Majumdar, Henley Liu, Myongseob Kim, Albert Shih-Huai Lin | 2021-07-06 |
| 10770430 | Package integration for memory devices | Myongseob Kim, Henley Liu, Jaspreet S. Gandhi | 2020-09-08 |
| 10692837 | Chip package assembly with modular core dice | Myongseob Kim, Henley Liu, Nui Chong | 2020-06-23 |
| 10431565 | Wafer edge partial die engineered for stacked die yield | Myongseob Kim, Henley Liu | 2019-10-01 |
| 10379155 | In-die transistor characterization in an IC | Ping-Chin Yeh, John K. Jennings, Rhesa Nathanael, Nui Chong, Daniel Chung | 2019-08-13 |
| 10262911 | Circuit for and method of testing bond connections between a first die and a second die | Yuqing Gong, Henley Liu, Myongseob Kim, Suresh Parameswaran, Boon Yong Ang | 2019-04-16 |
| 10103139 | Method and design of low sheet resistance MEOL resistors | Nui Chong, Jae-Gyung Ahn, Ping-Chin Yeh | 2018-10-16 |
| 10096502 | Method and apparatus for assembling and testing a multi-integrated circuit package | Gamal Refai-Ahmed, Suresh Ramalingam, Mohsen H. Mardi, Tien-Yu Lee, Ivor G. Barber +1 more | 2018-10-09 |
| 9412674 | Shielded wire arrangement for die testing | Myongseob Kim, Henley Liu, Sanjiv Stokes | 2016-08-09 |
| 8810269 | Method of testing a semiconductor structure | Yuqing Gong, Henley Liu, Myongseob Kim, Suresh Parameswaran, Boon Yong Ang | 2014-08-19 |
| 8802454 | Methods of manufacturing a semiconductor structure | Arifur Rahman, Henley Liu, Myongseob Kim, Dong Wook Kim | 2014-08-12 |