Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11488887 | Thermal enablement of dies with impurity gettering | Gamal Refai-Ahmed, Suresh Ramalingam, Boon Yong Ang, Toshiyuki Hisamura, Scott McCann +1 more | 2022-11-01 |
| 11073550 | Test vehicle for package testing | Yuqing Gong, Boon Yong Ang | 2021-07-27 |
| 10620644 | Systems and methods for on-die heat generation and temperature sensing | Boon Yong Ang, Sarayanan Balakrishnan | 2020-04-14 |
| 10302504 | On-die temperature sensing and digitization system | Boon Yong Ang, Ankur Jain | 2019-05-28 |
| 10262911 | Circuit for and method of testing bond connections between a first die and a second die | Yuqing Gong, Henley Liu, Myongseob Kim, Cheang-Whang Chang, Boon Yong Ang | 2019-04-16 |
| 8810269 | Method of testing a semiconductor structure | Yuqing Gong, Henley Liu, Myongseob Kim, Cheang-Whang Chang, Boon Yong Ang | 2014-08-19 |
| 8040164 | Circuits and methods for programming integrated circuit input and output impedances | Joseph Tzou, Morgan Whately, Thinh Tran | 2011-10-18 |
| 7728619 | Circuit and method for cascading programmable impedance matching in a multi-chip system | Joseph Tzou, Thinh Tran | 2010-06-01 |
| 7719908 | Memory having read disturb test mode | Joseph Tzou, Thinh Tran | 2010-05-18 |
| 7535772 | Configurable data path architecture and clocking scheme | Thinh Tran | 2009-05-19 |
| 7403446 | Single late-write for standard synchronous SRAMs | Thinh Tran, Joseph Tzou | 2008-07-22 |
| 7142477 | Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses | Thinh Tran, Joseph Tzou | 2006-11-28 |