Suresh Parameswaran has been granted 12 US patents while listed as an inventor at AMD . The first was granted in 2006 and the most recent in November 2022. Suresh Parameswaran ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list Suresh Parameswaran in Fremont, CA, US.
Patents per Year Patents granted per year, 2006 to 2022 Bar chart with a peak of 2 patents in 2010. peak 2 2006: 1 patents 2006 2008: 1 patents 2008 2009: 1 patents 2009 2010: 2 patents 2010 2011: 1 patents 2011 2014: 1 patents 2014 2019: 2 patents 2019 2020: 1 patents 2020 2021: 1 patents 2021 2022: 1 patents 2022
Issued Patents All Time
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Showing 1–12 of 12 patents
Patent # Title Co-Inventors Date Approx Value ⓘ
11488887 Thermal enablement of dies with impurity gettering Gamal Refai-Ahmed , Suresh Ramalingam , Boon Yong Ang , Toshiyuki Hisamura , Scott McCann +1 more 2022-11-01
11073550 Test vehicle for package testing Yuqing Gong , Boon Yong Ang 2021-07-27
$80,530,000
10620644 Systems and methods for on-die heat generation and temperature sensing Boon Yong Ang , Sarayanan Balakrishnan 2020-04-14
$21,268,000
10302504 On-die temperature sensing and digitization system Boon Yong Ang , Ankur Jain 2019-05-28
$41,882,000
10262911 Circuit for and method of testing bond connections between a first die and a second die Yuqing Gong , Henley Liu , Myongseob Kim , Cheang-Whang Chang , Boon Yong Ang 2019-04-16
$53,960,000
8810269 Method of testing a semiconductor structure Yuqing Gong , Henley Liu , Myongseob Kim , Cheang-Whang Chang , Boon Yong Ang 2014-08-19
$15,329,000
8040164 Circuits and methods for programming integrated circuit input and output impedances Joseph Tzou , Morgan Whately , Thinh Tran 2011-10-18
$3,107,000
7728619 Circuit and method for cascading programmable impedance matching in a multi-chip system Joseph Tzou , Thinh Tran 2010-06-01
$1,959,000
7719908 Memory having read disturb test mode Joseph Tzou , Thinh Tran 2010-05-18
$5,029,000
7535772 Configurable data path architecture and clocking scheme Thinh Tran 2009-05-19
$15,500,000
7403446 Single late-write for standard synchronous SRAMs Thinh Tran , Joseph Tzou 2008-07-22
$42,084,000
7142477 Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses Thinh Tran , Joseph Tzou 2006-11-28
$4,463,000
