| 9666255 |
Access methods and circuits for memory devices having multiple banks |
Thinh Tran, Jun Li |
2017-05-30 |
| 9640237 |
Access methods and circuits for memory devices having multiple channels and multiple banks |
Jun Li |
2017-05-02 |
| 8873264 |
Data forwarding circuits and methods for memory devices with write latency |
Thinh Tran |
2014-10-28 |
| 8705310 |
Access methods and circuits for memory devices having multiple banks |
Thinh Tran, Jun Li |
2014-04-22 |
| 8527802 |
Memory device data latency circuits and methods |
Thinh Tran |
2013-09-03 |
| 8358557 |
Memory device and method |
Thinh Tran, Jun Li |
2013-01-22 |
| 8149643 |
Memory device and method |
Thinh Tran, Jun Li |
2012-04-03 |
| 8095747 |
Memory system and method |
Bruce Barbara, Gabriel Li, Thinh Tran |
2012-01-10 |
| 8040164 |
Circuits and methods for programming integrated circuit input and output impedances |
Suresh Parameswaran, Morgan Whately, Thinh Tran |
2011-10-18 |
| 7728619 |
Circuit and method for cascading programmable impedance matching in a multi-chip system |
Suresh Parameswaran, Thinh Tran |
2010-06-01 |
| 7719908 |
Memory having read disturb test mode |
Suresh Parameswaran, Thinh Tran |
2010-05-18 |
| 7684257 |
Area efficient and fast static random access memory circuit and method |
Christopher Joseph Lee, Thinh Tran, Morgan Whately |
2010-03-23 |
| 7403446 |
Single late-write for standard synchronous SRAMs |
Suresh Parameswaran, Thinh Tran |
2008-07-22 |
| 7269772 |
Method and apparatus for built-in self-test (BIST) of integrated circuit device |
Jun Li, Thinh Tran |
2007-09-11 |
| 7196925 |
Memory array with current limiting device for preventing particle induced latch-up |
Jithender Majjiga, Morgan Whately, Thinh Tran |
2007-03-27 |
| 7146454 |
Hiding refresh in 1T-SRAM architecture |
Jun Li |
2006-12-05 |
| 7142477 |
Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses |
Thinh Tran, Suresh Parameswaran |
2006-11-28 |
| 5656861 |
Self-aligning contact and interconnect structure |
Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1997-08-12 |
| 5620919 |
Methods for fabricating integrated circuits including openings to transistor regions |
Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1997-04-15 |
| 5483104 |
Self-aligning contact and interconnect structure |
Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1996-01-09 |
| 5172211 |
High resistance Polysilicon load resistor |
Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1992-12-15 |
| 5168076 |
Method of fabricating a high resistance polysilicon load resistor |
Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1992-12-01 |
| 5166771 |
Self-aligning contact and interconnect structure |
Norman Godinho, Frank T. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1992-11-24 |
| 5124774 |
Compact SRAM cell layout |
Norman Godinho, Tsu-Wei F. Lee, Hsiang-Wen Chen, Richard F. Motta, Juine-Kai Tsang +2 more |
1992-06-23 |
