Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11854591 | Magnetic memory read circuit and calibration method therefor | Ebrahim Abedifard | 2023-12-26 |
| 11289142 | Nonvolatile memory sensing circuit including variable current source | Ebrahim Abedifard | 2022-03-29 |
| 11211107 | Magnetic memory read circuit and calibration method therefor | Ebrahim Abedifard | 2021-12-28 |
| 10818330 | Fast programming of magnetic random access memory (MRAM) | Mourad El Baraji | 2020-10-27 |
| 9666255 | Access methods and circuits for memory devices having multiple banks | Joseph Tzou, Jun Li | 2017-05-30 |
| 9455027 | Power management system for high traffic integrated circuit | Derwin W. Mattos | 2016-09-27 |
| 8873264 | Data forwarding circuits and methods for memory devices with write latency | Joseph Tzou | 2014-10-28 |
| 8705310 | Access methods and circuits for memory devices having multiple banks | Joseph Tzou, Jun Li | 2014-04-22 |
| 8675434 | High speed time interleaved sense amplifier circuits, methods and memory devices incorporating the same | Morgan Whately | 2014-03-18 |
| 8527802 | Memory device data latency circuits and methods | Joseph Tzou | 2013-09-03 |
| 8464145 | Serial interface devices, systems and methods | Edward L. Grivna, Gabriel Li | 2013-06-11 |
| 8358557 | Memory device and method | Joseph Tzou, Jun Li | 2013-01-22 |
| 8149643 | Memory device and method | Joseph Tzou, Jun Li | 2012-04-03 |
| 8095747 | Memory system and method | Bruce Barbara, Gabriel Li, Joseph Tzou | 2012-01-10 |
| 8040164 | Circuits and methods for programming integrated circuit input and output impedances | Suresh Parameswaran, Joseph Tzou, Morgan Whately | 2011-10-18 |
| 7728619 | Circuit and method for cascading programmable impedance matching in a multi-chip system | Joseph Tzou, Suresh Parameswaran | 2010-06-01 |
| 7719908 | Memory having read disturb test mode | Joseph Tzou, Suresh Parameswaran | 2010-05-18 |
| 7684257 | Area efficient and fast static random access memory circuit and method | Christopher Joseph Lee, Joseph Tzou, Morgan Whately | 2010-03-23 |
| 7535772 | Configurable data path architecture and clocking scheme | Suresh Parameswaran | 2009-05-19 |
| 7403446 | Single late-write for standard synchronous SRAMs | Suresh Parameswaran, Joseph Tzou | 2008-07-22 |
| 7269772 | Method and apparatus for built-in self-test (BIST) of integrated circuit device | Jun Li, Joseph Tzou | 2007-09-11 |
| 7196925 | Memory array with current limiting device for preventing particle induced latch-up | Joseph Tzou, Jithender Majjiga, Morgan Whately | 2007-03-27 |
| 7142477 | Memory interface system and method for reducing cycle time of sequential read and write accesses using separate address and data buses | Joseph Tzou, Suresh Parameswaran | 2006-11-28 |
| 6167321 | Interface module with protection circuit and method of protecting an interface | Ting Li Chan | 2000-12-26 |
| 5864252 | Synchronous circuit with improved clock to data output access time | Tsu-Wei F. Lee | 1999-01-26 |