| 12068257 |
Integrated circuit (IC) structure protection scheme |
Henley Liu, Yun Wu, Cheang-Whang Chang |
2024-08-20 |
| 11901338 |
Interwafer connection structure for coupling wafers in a wafer stack |
Henley Liu, Cheang-Whang Chang |
2024-02-13 |
| 11355412 |
Stacked silicon package assembly having thermal management |
Jaspreet S. Gandhi, Gamal Refai-Ahmed, Henley Liu, Tien-Yu Lee, Suresh Ramalingam +1 more |
2022-06-07 |
| 11205639 |
Integrated circuit device with stacked dies having mirrored circuitry |
Henley Liu, Cheang-Whang Chang |
2021-12-21 |
| 11114360 |
Multi-die device structures and methods |
Jaspreet S. Gandhi |
2021-09-07 |
| 11114344 |
IC die with dummy structures |
Hui-Wen Lin, Nui Chong, Henley Liu, Ping-Chin Yeh, Cheang-Whang Chang |
2021-09-07 |
| 11054461 |
Test circuits for testing a die stack |
Nui Chong, Amitava Majumdar, Cheang-Whang Chang, Henley Liu, Albert Shih-Huai Lin |
2021-07-06 |
| 10770430 |
Package integration for memory devices |
Henley Liu, Cheang-Whang Chang, Jaspreet S. Gandhi |
2020-09-08 |
| 10692837 |
Chip package assembly with modular core dice |
Henley Liu, Cheang-Whang Chang, Nui Chong |
2020-06-23 |
| 10529645 |
Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management |
Jaspreet S. Gandhi, Henley Liu, Tien-Yu Lee, Gamal Refai-Ahmed, Ferdinand F. Fernandez +2 more |
2020-01-07 |
| 10431565 |
Wafer edge partial die engineered for stacked die yield |
Henley Liu, Cheang-Whang Chang |
2019-10-01 |
| 10262911 |
Circuit for and method of testing bond connections between a first die and a second die |
Yuqing Gong, Henley Liu, Suresh Parameswaran, Cheang-Whang Chang, Boon Yong Ang |
2019-04-16 |
| 9412674 |
Shielded wire arrangement for die testing |
Henley Liu, Cheang-Whang Chang, Sanjiv Stokes |
2016-08-09 |
| 9236367 |
Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product |
Cinti X. Chen, Xiao-Yu Li, Mohsen H. Mardi |
2016-01-12 |
| 8987009 |
Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product |
Cinti X. Chen, Xiao-Yu Li, Mohsen H. Mardi |
2015-03-24 |
| 8810269 |
Method of testing a semiconductor structure |
Yuqing Gong, Henley Liu, Suresh Parameswaran, Cheang-Whang Chang, Boon Yong Ang |
2014-08-19 |
| 8802454 |
Methods of manufacturing a semiconductor structure |
Arifur Rahman, Henley Liu, Cheang-Whang Chang, Dong Wook Kim |
2014-08-12 |
| 8542514 |
Memory structure having SRAM cells and SONOS devices |
Sethuraman Lakshminarayanan |
2013-09-24 |
| 8329568 |
Semiconductor device and method for making the same |
Jae-Gyung Ahn, Ping-Chin Yeh, Zhiyuan Wu, John W. Cooksey |
2012-12-11 |
| 7960776 |
Transistor with floating gate and electret |
Nick Yu-Min Shen, Chungho Lee, Edwin C. Kan |
2011-06-14 |
