Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10868663 | Flexible wide-range and high bandwidth auxiliary clock and data recovery (CDR) circuit for transceivers | Mayank Raj, Adebabay M. Bekele, Parag Upadhyaya, Yohan Frans | 2020-12-15 |
| 10749532 | Method and apparatus for a phase locked loop circuit | Mayank Raj, Parag Upadhyaya, Yohan Frans, Kun-Yung Chang | 2020-08-18 |
| 10715153 | Multi-port inductors and transformers for accurately predicting voltage-controlled oscillator (VCO) frequency | Adebabay M. Bekele, Parag Upadhyaya, Jing Jing | 2020-07-14 |
| 10630301 | Temperature-dependent phase-locked loop (PLL) reset for clock synthesizers | Adebabay M. Bekele, Parag Upadhyaya | 2020-04-21 |
| 10623008 | Reconfigurable fractional-N frequency generation for a phase-locked loop | Parag Upadhyaya, Adebabay M. Bekele, Zhaoyin D. Wu | 2020-04-14 |
| 10498318 | Electrical circuits and methods to correct duty cycle error | Jaewook Shin, Parag Upadhyaya | 2019-12-03 |
| 10348310 | Programmable digital sigma delta modulator | Karim M Megawer, Parag Upadhyaya, Zhaoyin D. Wu | 2019-07-09 |
| 10270450 | Unified low power bidirectional port | Shaojun MA, Parag Upadhyaya | 2019-04-23 |
| 9755600 | Linear gain code interleaved automatic gain control circuit | Parag Upadhyaya, Kun-Yung Chang | 2017-09-05 |
| 9237041 | Data reception with feedback equalization for high and low data rates | Fu-Tai An, Yuan Chen | 2016-01-12 |
| 8928334 | On-chip noise measurement | Mayank Raj | 2015-01-06 |