| 12159057 |
Implementing data flows of an application across a memory hierarchy of a data processing array |
Chia-Jui Hsu, Mukund Sivaraman |
2024-12-03 |
|
| 12135990 |
Modeling and compiling tensor processing applications for a computing platform using multi-layer adaptive data flow graphs |
Chia-Jui Hsu, Mukund Sivaraman |
2024-11-05 |
|
| 11687327 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform |
Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig |
2023-06-27 |
|
| 11645053 |
Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices |
Akella Sastry, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddharth Rele |
2023-05-09 |
|
| 11281440 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform |
Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig |
2022-03-22 |
|
| 11204745 |
Dataflow graph programming environment for a heterogenous processing system |
Shail Aditya Gupta, Samuel R. Bayliss, Ralph D. Wittig, Philip B. James-Roxby, Akella Sastry |
2021-12-21 |
$86,928,000 |
| 11188312 |
Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices |
Akella Sastry, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddharth Rele |
2021-11-30 |
$61,864,000 |
| 10891414 |
Hardware-software design flow for heterogeneous and programmable devices |
Shail Aditya Gupta, Srinivas Beeravolu, Dinesh K. Monga, Pradip K. Jha, Vishal Suthar +2 more |
2021-01-12 |
$57,179,000 |
| 10860766 |
Compilation flow for a heterogeneous multi-core architecture |
Mukund Sivaraman, Shail Aditya Gupta, Akella Sastry, Rishi Surendran, Philip B. James-Roxby +3 more |
2020-12-08 |
$24,793,000 |
| 10802807 |
Control and reconfiguration of data flow graphs on heterogeneous computing platform |
Chia-Jui Hsu, Shail Aditya Gupta, Samuel R. Bayliss, Philip B. James-Roxby, Ralph D. Wittig |
2020-10-13 |
$57,700,000 |
| 10635769 |
Hardware and software event tracing for a system-on-chip |
Samuel A. Skalicky, L. James Hwang |
2020-04-28 |
$32,103,000 |
| 9880966 |
Encapsulating metadata of a platform for application-specific tailoring and reuse of the platform in an integrated circuit |
L. James Hwang, Sundararajarao Mohan, Jorge Ernesto Carrillo, Hua Sun |
2018-01-30 |
$13,591,000 |
| 9805152 |
Compilation of system designs |
Jorge Ernesto Carrillo, L. James Hwang, Sundararajarao Mohan, Hua Sun |
2017-10-31 |
$21,557,000 |
| 9652570 |
Automatic implementation of a customized system-on-chip |
L. James Hwang, Sundararajarao Mohan, Jorge Ernesto Carrillo, Hua Sun, Tom Shui +1 more |
2017-05-16 |
$14,899,000 |
| 9223921 |
Compilation of HLL code with hardware accelerated functions |
Jorge Ernesto Carrillo, L. James Hwang, Hua Sun, Sundararajarao Mohan |
2015-12-29 |
$7,580,000 |
| 9147024 |
Hardware and software cosynthesis performance estimation |
Hua Sun, Sundararajarao Mohan, L. James Hwang, Yogesh Laxmikant Chobe |
2015-09-29 |
$10,791,000 |
| 8762916 |
Automatic generation of a data transfer network |
L. James Hwang, Sundararajarao Mohan, Hua Sun |
2014-06-24 |
$26,755,000 |
| 7107199 |
Method and system for the design of pipelines of processors |
Robert Schreiber, Shail Aditya Gupta, Santosh Abraham, Bantwal R. Rau |
2006-09-12 |
$7,515,000 |
| 6772106 |
Retargetable computer design system |
Scott Mahlke, Santosh Abraham |
2004-08-03 |
$8,945,000 |
| 6766445 |
Storage system for use in custom loop accelerators and the like |
Michael Schlansker, Shail Aditya Gupta |
2004-07-20 |
$10,517,000 |
| 6651222 |
Automatic design of VLIW processors |
Shail Aditya Gupta, B. Ramakrishna Rau, Michael Schlansker |
2003-11-18 |
$9,447,000 |
| 6581187 |
Automatic design of VLIW processors |
Shail Aditya Gupta, B. Ramakrishna Rau, Michael Schlansker |
2003-06-17 |
$19,625,000 |
| 6507947 |
Programmatic synthesis of processor element arrays |
Robert Schreiber, B. Ramakrishna Rau, Shail Aditya Gupta, Sadun Anik |
2003-01-14 |
$33,970,000 |
| 6408428 |
Automated design of processor systems using feedback from internal measurements of candidate systems |
Michael Schlansker, Greg Snider, Shail Aditya Gupta, Scott Mahlke, Santosh Abraham |
2002-06-18 |
$27,526,000 |
| 6385757 |
Auto design of VLIW processors |
Shail Aditya Gupta, B. Ramakrishna Rau, Michael Schlansker |
2002-05-07 |
$23,164,000 |
