Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11645053 | Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices | Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddharth Rele | 2023-05-09 |
| 11615052 | Packet identification (ID) assignment for routing network | Rishi Surendran, Abnikant Singh | 2023-03-28 |
| 11204745 | Dataflow graph programming environment for a heterogenous processing system | Shail Aditya Gupta, Samuel R. Bayliss, Vinod K. Kathail, Ralph D. Wittig, Philip B. James-Roxby | 2021-12-21 |
| 11188312 | Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices | Vinod K. Kathail, L. James Hwang, Shail Aditya Gupta, Vidhumouli Hunsigida, Siddharth Rele | 2021-11-30 |
| 11138019 | Routing in a compilation flow for a heterogeneous multi-core architecture | Henri Fraisse, Rishi Surendran, Abnikant Singh | 2021-10-05 |
| 10860766 | Compilation flow for a heterogeneous multi-core architecture | Mukund Sivaraman, Shail Aditya Gupta, Rishi Surendran, Philip B. James-Roxby, Samuel R. Bayliss +3 more | 2020-12-08 |
| 10228919 | Demand-driven algorithm to reduce sign-extension instructions included in loops of a 64-bit computer program | Yuan Lin | 2019-03-12 |
| 7707566 | Software development infrastructure | Vinod Grover, Charles Mitchell, David Gillies, Mark Roberts, Mark Ronald Plesko +4 more | 2010-04-27 |
| 7308680 | Intermediate representation for multiple exception handling models | Vinod Grover | 2007-12-11 |
| 7120898 | Intermediate representation for multiple exception handling models | Vinod Grover | 2006-10-10 |